TFT-LCD array substrate and method of manufacturing the same

1. A thin film transistor liquid crystal display (TFT-LCD) array substrate, comprising:

a plurality of gate lines and a plurality of data lines formed on a substrate,

wherein the gate lines and the data lines define a plurality of pixel regions, and

wherein, in each of the pixel regions, a pixel electrode, a thin film transistor and a first light blocking bar are formed, a second light blocking bar is formed over the first light blocking bar, and the second light blocking bar is formed between the pixel electrode of the pixel region and the data line for the pixel region.

2. The TFT-LCD array substrate of claim 1 , wherein

the first light blocking bar and the gate lines are formed in a same layer and formed in a same one patterning process; and

the second light blocking bar and the data lines are formed in a same layer and formed in a same one patterning process.

3. The TFT-LCD array substrate of claim 2 , wherein

a semiconductor thin film and a doped semiconductor thin film are retained under the second light blocking bar and the data lines.

4. The TFT-LCD array substrate of claim 2 , wherein

the first light blocking bar is connected with the second light blocking bar by a first connection stripe.

5. The TFT-LCD array substrate of claim 4 , wherein

two first light blocking bars in two adjacent pixel regions in a vertical direction are connected by a second connection stripe, and

the first light blocking bar and the second light blocking bar respectively in two adjacent pixel regions in a horizontal direction are connected by a third connection stripe.

6. The TFT-LCD array substrate of claim 5 , wherein

on one side of each of the pixel regions, a first through hole is formed in a passivation layer on a first end of the second light blocking bar, a second through hole is formed in a gate insulation layer and the passivation layer on a first end of the first light blocking bar adjacent to the first through hole, and the first connection stripe connects the first light blocking bar with the second light blocking bar via the first through hole and the second through hole.

7. The TFT-LCD array substrate of claim 5 , wherein

on one side of each of the pixel regions, a third through hole is formed in a gate insulation layer and a passivation layer on a second end of the first light blocking bar, and the second connection stripe connects two first light blocking bars in two adjacent pixel regions in a vertical direction via the second through hole and the third through hole.

8. The TFT-LCD array substrate of claim 5 , wherein

on the other side of each pixel region opposite to the first connection stripe that is positioned on one side of the pixel region, a fourth through hole is formed in a passivation layer on a second end of the second light blocking bar, and the third connection stripe connects the first light blocking bar with the second light blocking bar in two adjacent pixel regions in a horizontal direction via the third through hole and the fourth through hole.

9. The TFT-LCD array substrate of claim 5 , wherein

the first connection stripe, the second connection stripe, the third connection stripe and the pixel electrode in each of the pixel regions are formed in a same layer and a same one patterning process.

10. The TFT-LCD array substrate of claim 1 , further comprising a common electrode in each of the pixel regions, wherein the common electrode and the first light blocking bar are an integral structure connected with each other.

11. The TFT-LCD array substrate of claim 2 , further comprising a common electrode in each of the pixel regions, wherein the common electrode and the first light blocking bar are an integral structure connected with each other.

12. The TFT-LCD array substrate of claim 1 , wherein a width of the second light blocking bar is 40%˜60% of a width of the first light blocking bar.

13. A method for manufacturing a thin film transistor liquid crystal display (TFT-LCD) array substrate comprising a plurality of pixel regions, the method comprising:

Step 1 of forming a gate metal thin film on a substrate and forming a gate line, a gate electrode, and a first light blocking bar are formed for each pixel region by patterning;

Step 2 of forming a gate insulation layer, a semiconductor thin film, a doped semiconductor thin film and a source drain metal thin film on the resultant substrate obtained after step 1, an island-like active layer, a data line, a drain electrode, a source electrode, a thin film transistor (TFT) channel region and a second light blocking bar are formed for the pixel region by patterning, wherein the second light blocking bar is disposed over the first light blocking bar, and the gate line and the data line define the respective pixel region;

Step 3 of forming a passivation layer on the resultant substrate obtained after step 2 and a passivation layer through hole are formed for the pixel region by patterning; and

Step 4 of forming a transparent conductive thin film on the resultant substrate obtained after step 3, and a pixel electrode is formed for the pixel region by patterning, wherein the pixel electrode is connected with the drain electrode via the passivation through holes,

wherein the second light blocking bar is formed between the pixel electrode of the pixel region and the data line.

14. The method of claim 13 , wherein a width of the second light blocking bar is 40%˜60% of a width of the first light blocking bar.

15. The method of claim 13 , wherein

the step 3 further comprises, on one side of each pixel region, forming a first through hole in the passivation layer on a first end of the second light blocking bar, and a second through hole is formed in the gate insulation layer and the passivation layer on a first end of the first light blocking bar adjacent to the first through hole; and

the step 4 further comprises forming a first connection stripe along with the pixel electrode by patterning, wherein the first connection stripe connects the first light blocking bar and the second light blocking bar via the first through hole and the second through hole.

16. The method of claim 15 , wherein

the step 3 further comprises, on the one side of each pixel region, forming a third through hole in the gate insulation layer and the passivation layer on a second end of the first light blocking bar; and

the step 4 further comprises forming a second connection stripe by a patterning process, wherein the second connection stripe connects two first light blocking bars in two adjacent pixel regions via the second through hole and the third through hole.

17. The method of claim 16 , wherein

the step 3 further comprises, on the other side of each pixel region, forming a fourth through hole in the passivation layer on a second end of the second light blocking bar; and

the step 4 further comprises forming a third connection stripe by patterning, wherein the third connection stripe connects the first light blocking bar and the second light blocking bar in two adjacent pixel regions via the third through hole and the fourth through hole.

18. The method of claim 16 , wherein

the step 3 further comprises, on the one side of the pixel region, forming a fifth through hole in the passivation layer on a second end of the second light blocking bar; and

the second connection stripe also passes through the fifth through hole.

19. The method of claim 13 , wherein

the step 3 further comprises forming the passivation layer through hole above the drain electrode.

20. The method of claim 13 , wherein

in the step 1, in each of the pixel regions, a common electrode is further formed, and the common electrode and the first light blocking bar are connected an integrate structure.