IP Library Granted Patent US 8,781,028
Granted Patent B2
US 8,781,028 · App. 12/724,586 · Granted Jul 15, 2014

Integrated receiving circuit and method for radiofrequency and high speed signals

Inventors: Edoardo Charbon (Echandens, CH); Marek Gersbach (Lausanne, CH); Maximilian Sergio (Lausanne, CH)
Assignee: Ecole Polytechnique Federale de Lausanne (EPFL)
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Quick Facts
Patent No.
US 8,781,028
App. No.
12/724,586
Granted
Jul 15, 2014
Kind
B2
Abstract

Integrated receiving circuit for radiofrequency signals an amplifying element using the multiplication zone of a reverse biased semiconductor junction operating in Geiger mode for amplifying an input radiofrequency signal (Vin) and converting it into a digital signal. And a digital part for digitally processing the digital signal.

Claims (19)

1. An integrated receiving circuit for radio frequency and high speed signals, comprising:

an amplifying element using the multiplication zone of a reverse biased semiconductor junction operating in Geiger mode for amplifying an input radio frequency signal and converting said input radio frequency signal into a digital signal, wherein the amplifying element comprises an injector which can receive an input radio frequency signal and can convert the received input radio frequency signal into input charge carriers which are injected into the multiplication zone of the reverse biased semiconductor junction operating in Geiger mode; and

a digital circuitry for digitally processing said digital signal.

2. The integrated receiving circuit of claim 1 , further comprising a recharge circuit for recharging said multiplication zone after an avalanche.

3. The integrated circuit of claim 2 , further comprising a clock circuit periodically turning on a switch for recharging said multiplication zone.

4. The integrated circuit of claim 2 , comprising an avalanche detection circuit for commanding a switch to recharge said multiplication zone when an avalanche has been detected.

5. The integrated circuit of claim 1 , further comprising an active or passive quenching circuit for quenching the signal delivered by said semiconductor junction.

6. The integrated circuit of claim 1 , further comprising a guard ring around said multiplication zone.

7. The integrated circuit of claim 6 , comprising a circuit for injecting charges into said guard ring to trigger avalanches in said multiplication zone.

8. The integrated circuit of claim 6 , comprising an injection junction outside said guard ring for injecting charges during the recharge of said multiplication zone.

9. The integrated circuit of claim 1 , comprising a shield for preventing photons to trigger an avalanche, wherein charges are injected directly into said shield.

10. The integrated circuit of claim 1 , comprising an antenna, said multiplication zone being close to the focal centre of said antenna to capture electromagnetic power received by the antenna for triggering an avalanche.

11. The integrated circuit of claim 1 , said digital circuitry comprising at least one of a digital mixing and demodulating circuit for either mixing or demodulating said digital signal.

12. The integrated circuit of claim 1 , wherein said amplifying element and said digital part are both CMOS integrated.

13. A method for processing a radio frequency signal, comprising the steps of:

receiving an input radio frequency signal;

converting the received input radio frequency signal into input charge carriers;

injecting said input charge carriers into the multiplication zone of the reverse biased semiconductor junction operating in Geiger mode, to form an avalanche in a reverse biased semiconductor junction operating in Geiger mode and to output a digital signal, and

digital processing said digital signal.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2015
From: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 037305/0155 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2010
From: CHARBON, EDOARDO; GERSBACH, MAREK; SERGIO, MAXIMILIAN
To: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE
Reel/Frame 024324/0873 →
Continuity (2)
Continuation PCTEP2007059995 · Sep 20, 2007
Related Publication 20100208845A1 · Aug 19, 2010