Decoding algorithm for frequency shift key communications
View Patent ↗A method and apparatus for decoding binary frequency shift key signals in which an exclusive-OR of the sign of a real waveform with a sign of the imaginary waveform at a time shortly after the real (or, alternatively, the imaginary) waveform crosses zero is used to determine a bit represented by the signal. In some embodiments, particularly those in which the bit period is about one-half of the carrier signal frequency, both the real and imaginary waveforms are monitored to detect the zero crossing in order to account for the situation in which data transitions prevent zero-crossings on one of the waveforms.
1. A method for processing a frequency shift key signal comprising the steps of:
mixing the frequency shift key signal with in-phase and quadrature components of a signal at a nominal center frequency corresponding to the frequency shift key signal to produce a mixed in-phase component and a mixed quadrature component;
filtering mixed in-phase component and the mixed quadrature component to produce a difference in-phase component and a difference quadrature component; and
ascertaining a logical symbol indicated by the frequency shift key signal at a point in time by determining whether the difference in-phase component leads or lags the difference quadrature component at the point in time, wherein the determining comprises:
monitoring both the difference in-phase component and the difference quadrature component to detect a zero crossing of one of the difference in-phase component and the difference quadrature component;
performing an exclusive-or operation on a sign of the difference in-phase component and a sign of the difference quadrature component at a point in time that is within the interval between the zero crossing detected in the detecting step and one fourth of a period of the component for which the zero crossing is detected in the detecting step;
when the zero crossing is detected for the difference in-phase component, ascertaining the logical symbol directly and solely from the result of the exclusive-or operation on the sign of the difference in-phase component and the sign of the difference quadrature component without calculating a negative of the exclusive-or of the sign of the difference in-phase component and the difference quadrature component; and
when the zero crossing is detected for the difference quadrature component, calculating a negative of the exclusive-or of the sign of the difference in-phase component and the difference quadrature component and ascertaining the logical symbol directly from the negative of the result of the exclusive-or operation on the sign of the difference in-phase component and the sign of the difference quadrature component.
2. The method of claim 1 , wherein the determining step is repeated for a plurality of points in time.
3. The method of claim 1 , wherein the component for which the zero crossing is detected is the difference in-phase component.
4. The method of claim 1 , wherein the component for which the zero crossing is detected is the difference quadrature component.
5. A system for processing a frequency shift key signal comprising:
a first mixer for mixing the frequency shift key signal with an in-phase component of a signal at a nominal center frequency corresponding to the frequency shift key signal to produce a mixed in-phase component;
a second mixer for mixing the frequency shift key signal with a quadrature component of a signal at a nominal center frequency corresponding to the frequency shift key signal to produce a mixed quadrature component;
a filter circuit operable to input an output from the first mixer and the second mixer, the filter circuit being operable to filter the mixed in-phase component and the mixed quadrature component to produce a difference in-phase component and a difference quadrature component; and
a logic unit connected to the filter circuit, the logic unit being configured to ascertain a logical symbol indicated by the frequency shift key signal at a point in time by determining whether the difference in-phase component leads or lags the difference quadrature component at the point in time, wherein the logic unit is configured to perform the determining by:
monitoring both the difference in-phase component and the difference quadrature component to detect a zero crossing of one of the difference in-phase component and the difference quadrature component;
performing an exclusive-or operation on a sign of the difference in-phase component and a sign of the difference quadrature component at a point in time that is within the interval between the zero crossing detected in the detecting step and one fourth of a period of the component for which the zero crossing is detected in the detecting step;
when the zero crossing is detected for the difference in-phase component, ascertaining the logical symbol directly and solely from the result of the exclusive-or operation on the sign of the difference in-phase component and the sign of the difference quadrature component without calculating a negative of the exclusive-or of the sign of the difference in-phase component and the difference quadrature component; and
when the zero crossing is detected for the difference quadrature component, calculating a negative of the exclusive-or of the sign of the difference in-phase component and the difference quadrature component and ascertaining the logical symbol directly from the negative of the result of the exclusive-or operation on the sign of the difference in-phase component and the sign of the difference quadrature component.
6. The system of claim 5 , wherein the logic unit is a microprocessor.
7. The system of claim 5 , in which the filter circuit comprises a finite impulse response filter that processes both the mixed in-phase component and the mixed quadrature component.
8. The system of claim 5 , further comprising an analog-digital-converter operable to input an analog frequency shift key signal and output digitized samples of the frequency shift key signal to the mixers.
9. The system of claim 8 , further comprising a numerically controlled oscillator connected to the mixers and configured to generate a signal at a nominal center frequency corresponding to the frequency shift key signal.
10. The system of claim 5 , wherein the determining step is repeated for a plurality of points in time.
11. The system of claim 5 , wherein the component for which the zero crossing is detected is the difference in-phase component.
12. The system of claim 5 , wherein the component for which the zero crossing is detected is the difference quadrature component.