IP Library Granted Patent US 8,294,306
Granted Patent B2
US 8,294,306 · App. 12/725,053 · Granted Oct 23, 2012

DC capacitor balancing

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,294,306
App. No.
12/725,053
Granted
Oct 23, 2012
Kind
B2
Abstract

Methods and devices for balancing voltages of capacitors in an electronic circuit are provided. The device includes a chopper circuit having a chopper inductor. Further, the chopper circuit may detect voltages across capacitors as well as an output current of the electronic circuit. In addition, the device may include a chopper control unit receiving the output current then generating a signal representing charging of the chopper inductor based on the output current. Also, the chopper control unit may receive the voltages across the capacitors and detect an imbalance between the voltages based on a polarity of the output current. Additionally, the chopper control unit may transfer of charge between the two capacitors, using the chopper inductor. Further, the chopper inductor is substantially discharged, during the transfer of charge between the capacitors.

Claims (55)

1. A device for balancing voltages of capacitors in an electronic circuit, the device comprising:

a chopper circuit including a chopper inductor, the chopper circuit measuring a first voltage of a first capacitor of the electronic circuit, a second voltage of a second capacitor of the electronic circuit, and an output current of the electronic circuit; and

a chopper control unit receiving the output current and generating a signal representing charging of the chopper inductor based on the output current, the signal having a switching frequency and a duty cycle, the chopper control unit receiving the first voltage and the second voltage and detecting an imbalance between the first voltage and the second voltage based on a polarity of the output current, the chopper control unit controlling transfer of charge between the first capacitor and the second capacitor using the chopper inductor based on the imbalance between the first voltage and second voltage and based on the signal representing charging of the chopper inductor.

2. The device of claim 1 , wherein the chopper inductor is substantially discharged based on the switching frequency and the duty cycle during the transfer of charge between the first capacitor and the second capacitor.

3. The device of claim 1 , wherein the chopper circuit includes at least one switch and at least one diode to transfer charge between the first capacitor and the second capacitor using the chopper inductor.

4. The device of claim 3 , further comprising a chopper pulse generator receiving the switching frequency and the duty cycle, and configured to control a first switch, a first diode, a second switch, and a second diode to transfer charge between the first capacitor to the second capacitor.

5. The device according to claim 1 , wherein the signal representing charging of the chopper inductor is a substantially triangular carrier waveform based on a voltage of the chopper inductor, inductance of the chopper inductor, and the output current such that the switching frequency and the duty cycle of the substantially triangular carrier waveform allows for the chopper inductor to be substantially discharged when transferring charge between the first capacitor and the second capacitor, wherein the switching frequency and duty cycle is based on the output current and an error signal based on the first voltage and a reference voltage.

6. The device according to claim 1 , wherein the imbalance of the first voltage and the second voltage is based on a reference voltage of at least one of the first capacitor and the second capacitor.

7. The device according to claim 1 , further comprising a computing device coupled to the chopper control unit, the computing device further controlling the transfer of charge between the first capacitor and the second capacitor.

8. A method for balancing voltages of capacitors in an electronic circuit, the method comprising:

receiving a first voltage of a first capacitor of the electronic circuit, a second voltage of a second capacitor of the electronic circuit, and an output current of the electronic circuit;

generating a signal representing charging of an inductor based on the output current, the signal having a switching frequency and a duty cycle;

detecting an imbalance between the first voltage and the second voltage based on a polarity of the output current; and

based on the imbalance between the first voltage and the second voltage and based on the signal representing charging of the inductor, causing transfer of charge between the first capacitor and the second capacitor using the inductor.

9. The method of claim 8 , wherein the inductor is substantially discharged based on the switching frequency and the duty cycle during transfer of charge between the first capacitor and the second capacitor and the signal representing charge of the inductor is a substantially triangular carrier waveform.

10. The method of claim of 8 , further comprising:

receiving the first voltage across the first capacitor at a first time instance;

generating a first error signal value based on the first voltage and a reference voltage;

comparing the first error signal value to the signal representing charging of the inductor; and

causing a first current to flow from the first capacitor to the inductor.

11. The method of claim of 10 , further comprising:

receiving a third voltage across the first capacitor at a second time instance;

generating a second error signal value based on the third voltage and the reference voltage;

comparing the second error signal value to the signal representing charging of the inductor; and

causing a second current to flow from the inductor to the second capacitor.

12. The method of claim 10 further comprising:

closing a first switch to cause the first current to flow from the first capacitor to the inductor, thereby discharging the first capacitor and charging the inductor; and

opening the first switch to cause the second current to flow from the inductor through a first diode to the second capacitor thereby discharging the inductor and charging the second capacitor.

13. The method of claim 8 further comprising:

calculating the switching frequency and the duty cycle of the substantially triangular carrier waveform based on the output current; and

providing the switching frequency and a duty cycle of the substantially triangular carrier waveform.

14. The method of claim 8 further comprising controlling transfer of charge between the first capacitor and the second capacitor using a computing device.

15. A computer-readable medium having stored thereon, computer-executable instructions that, when executed by a device, cause the device to perform functions comprising:

receiving a first voltage of a first capacitor of an electronic circuit, a second voltage of a second capacitor of the electronic circuit, and an output current of the electronic circuit;

generating a signal representing charging of an inductor based on the output current, the signal having a switching frequency and a duty cycle;

detecting an imbalance between the first voltage and the second voltage based on a polarity of the output current;

based on the imbalance between the first voltage and the second voltage and based on the signal representing charging of the inductor, causing transfer of charge between the first capacitor and the second capacitor using the inductor, wherein the inductor is substantially discharged based on the switching frequency and the duty cycle during transfer of charge between the first capacitor and the second capacitor;

wherein the signal representing charge of the inductor is a substantially triangular carrier waveform.

16. The computer-readable medium of claim 15 , wherein the inductor is substantially discharged based on the switching frequency and the duty cycle during transfer of charge between the first capacitor and the second capacitor.

17. The computer-readable medium of claim 15 , wherein the functions further comprise:

receiving the first voltage across the first capacitor at a first time instance;

generating a first error signal value based on the first voltage and a reference voltage;

comparing the first error signal value to the signal representing charging of the inductor; and

causing a first current to flow from the first capacitor to the inductor.

18. The computer-readable medium of claim 17 , wherein the functions further comprise:

receiving a third voltage across the first capacitor at a second time instance;

generating a second error signal value based on the third voltage and the reference voltage;

comparing the second error signal value to the signal representing charging of the chopper inductor; and

causing a second current to flow from the inductor to the second capacitor.

19. The computer-readable medium of claim 18 , wherein the functions further comprise:

closing a first switch to cause the first current to flow from the first capacitor to the inductor, thereby discharging the first capacitor and charging the inductor; and

opening the first switch to cause the second current to flow from the chopper inductor through a first diode of the chopper circuit to the second capacitor thereby discharging the inductor and charging the second capacitor.

20. The computer-readable medium of claim 15 , wherein the functions further comprise:

calculating the switching frequency and the duty cycle of the substantially triangular carrier waveform based on the output current; and

providing the switching frequency and a duty cycle of the substantially triangular carrier waveform.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jul 31, 2019
From: CRESTLINE DIRECT FINANCE, L.P.
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 049924/0794 →
SECURITY INTEREST Recorded Jan 29, 2019
From: EMPIRE TECHNOLOGY DEVELOPMENT LLC
To: CRESTLINE DIRECT FINANCE, L.P.
Reel/Frame 048373/0217 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2010
From: KUMAR, MAHESH; SRIDHARAN, SRIKANTHAN; KRISHNAN, JAGANATH
To: INDIAN INSTITUTE OF TECHNOLOGY MADRAS
Reel/Frame 024088/0510 →