Method of designing a template pattern, method of manufacturing a template and method of manufacturing a semiconductor device
View Patent ↗A method of designing a template pattern used for imprint lithography, includes generating data of a dummy template pattern to be formed in a third area between first and second areas of a template based on data of a design pattern of the template, the data of the dummy template pattern being generated so that a third surface area ratio showing a ratio of a surface area of the third area to an area of the third area is set smaller than a first surface area ratio showing a ratio of a surface area of the first area to an area of the first area and larger than a second surface area ratio showing a ratio of a surface area of the second area to an area of the second area.
1. A computer-implemented method of designing a template pattern used for imprint lithography, comprising:
generating, by a computer, data of a dummy template pattern to be formed in a third area between first and second areas of a template based on data of a design pattern of the template,
the data of the dummy template pattern being generated so that a third surface area ratio showing a ratio of a surface area of the third area to an area of the third area is set to be:
smaller than a first surface area ratio showing a ratio of a surface area of the first area to an area of the first area, and
larger than a second surface area ratio showing a ratio of a surface area of the second area to an area of the second area.
2. The method according to claim 1 , wherein generating the data of the dummy template pattern includes:
calculating the first surface area ratio based on the data of the design pattern;
calculating the second surface area ratio based on the data of the design pattern; and
generating the data of the dummy template pattern based on the first and second surface area ratios.
3. The method according to claim 1 , wherein the first area is included in a chip area.
4. The method according to claim 1 , wherein the second area is included in an interchip area.
5. The method according to claim 1 , wherein the second area has no pattern.
6. The method according to claim 1 , wherein a pitch of a dummy template pattern of the third area is larger than that of a template pattern of the first area.
7. The method according to claim 1 , wherein a width of a dummy template pattern of the third area is larger than that of a template pattern of the first area.
8. The method according to claim 1 , wherein the surface area ratio of the third area is constant.
9. The method according to claim 1 , wherein the surface area ratio of the third area changes.
10. The method according to claim 1 , wherein the third area includes a first sub-area and a second sub-area between the second area and the first sub-area, and
a fourth surface area ratio showing a ratio of a surface area of the first sub-area to an area of the first sub-area is smaller than the first surface area ratio, and
a fifth surface area ratio showing a ratio of a surface area of the second sub-area to an area of the second sub-area is smaller than the fourth surface area ratio, and larger than the second surface area ratio.
11. The method according to claim 1 , wherein the surface area ratio of the third area decreases from the first area toward the second area.
12. A method of manufacturing a template, comprising:
forming a template pattern designed using the method according to claim 1 in a template substrate.
13. A method of manufacturing a semiconductor device, comprising:
transferring a pattern formed in the template manufactured using the method according to claim 12 to an imprint material layer on a substrate.