Forward error correction (FEC) scheme for communications
View Patent ↗Forward error correction (FEC) scheme for communications. Appropriate selection/arrangement of bits of an information bit sequence undergo one or more types of subsequent encoding to generate a coded bit sequence that may subsequently undergo appropriate processing to generate a continuous time signal to be launched within a communication channel. In some embodiments, an information bit sequence, after being partitioning into a number of information bit groups, initially undergoes a first encoding within a first encoding module thereby generating a number of redundancy/parity bit groups (e.g., e.g., each redundancy/parity bit group corresponding to one of the information bit groups). Then, after performing any desired and appropriate selection/arrangement of bits within the redundancy/parity bit groups and the information bit groups, second encoding within a second encoding module is performed thereon to generate additional redundancy/parity bits. In addition, interleaving may be performing at various stages of the encoding processing.
1. An apparatus, comprising:
a matrix formatting module to:
partition a plurality of bits into a plurality of bit groups, such each of the plurality of bit groups respectively includes a consecutive subset of the plurality of bits; and
arrange the plurality of bit groups and at least one fill bit in accordance with a predetermined pattern to generate a plurality of matrix formatted bits that includes a predetermined plurality of bits such that at least one of the plurality of bit groups spans more than one matrix row of the plurality of matrix formatted bits;
an encoder module, communicatively coupled to the matrix formatting module, to perform at least one of:
encode bits within a plurality of rows of the plurality of matrix formatted bits to generate a first plurality of parity bits; and
encode bits within a plurality of columns of the plurality of matrix formatted bits to generate a second plurality of parity bits; and
a transmit driver, communicatively coupled to the encoder module, to arrange the plurality of matrix formatted bits and at least one of the first plurality of parity bits and the second plurality of parity bits to generate an output bit sequence.
2. The apparatus of claim 1 , wherein:
the encoder module to employ a Reed-Solomon (RS) code, a turbo code, a turbo trellis code modulation (TTCM) code, a LDPC (Low Density Parity Check) code, or a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code.
3. The apparatus of claim 1 , further comprising:
an interleaver module, communicatively coupled to the encoder module, to interleave at least one of:
the plurality of matrix formatted bits;
bits within a row of the plurality of matrix formatted bits;
bits within a column of the plurality of matrix formatted bits;
the first plurality of parity bits; and
the second plurality of parity bits.
4. The apparatus of claim 1 , wherein:
bits within at least one of the plurality of bit groups are emplaced within a plurality of rows of the plurality of matrix formatted bits.
5. The apparatus of claim 1 , wherein:
the encoder module being a multi-code encoder module to employ a first error correction code (ECC) to encode a first subset of the plurality of matrix formatted bits and employ a second ECC to encode a second subset of the plurality of matrix formatted bits.
6. The apparatus of claim 1 , further comprising:
at least one additional encoder module, communicatively coupled to the matrix formatting module, to encode a plurality of information bits to generate the plurality of bits.
7. The apparatus of claim 6 , wherein:
the at least one additional encoder module employs a Reed-Solomon (RS) code, a turbo code, a turbo trellis code modulation (TTCM) code, a LDPC (Low Density Parity Check) code, or a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code.
8. The apparatus of claim 1 , wherein:
the encoder module to encode at least one of the first plurality of parity bits and the second plurality of parity bits to generate a third plurality of parity bits; and
the transmit driver also to arrange the third plurality of parity bits in accordance with generating the output bit sequence.
9. The apparatus of claim 1 , wherein:
the matrix formatting module to arrange the plurality of bit groups and at least one fill bit in accordance with the predetermined pattern to generate the plurality of matrix formatted bits.
10. The apparatus of claim 1 , wherein:
the apparatus being a operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
11. An apparatus, comprising:
a first encoder module to encode a plurality of information bits to generate a plurality of bits;
a matrix formatting module, communicatively coupled to the first encoder module, to:
partition the plurality of bits into a plurality of bit groups, such each of the plurality of bit groups respectively includes a consecutive subset of the plurality of bits; and
arrange the plurality of bit groups and at least one fill bit in accordance with a predetermined pattern to generate a plurality of matrix formatted bits that includes a predetermined plurality of bits such that at least one of the plurality of bit groups spans more than one matrix row of the plurality of matrix formatted bits;
a second encoder module, communicatively coupled to the matrix formatting module, to:
encode bits within a plurality of rows of the plurality of matrix formatted bits to generate a first plurality of parity bits;
encode bits within a plurality of columns of the plurality of matrix formatted bits to generate a second plurality of parity bits; and
encode at least one of the first plurality of parity bits and the second plurality of parity bits to generate a third plurality of parity bits; and
a transmit driver, communicatively coupled to the second encoder module, to arrange the plurality of matrix formatted bits and at least one of the first plurality of parity bits and the second plurality of parity bits to generate an output bit sequence.
12. The apparatus of claim 11 , wherein:
at least one of the first encoder module and the second encoder module employs a Reed-Solomon (RS) code, a turbo code, a turbo trellis code modulation (TTCM) code, a LDPC (Low Density Parity Check) code, or a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code.
13. The apparatus of claim 11 , further comprising:
an interleaver module, communicatively coupled to the second encoder module, to interleave at least one of:
the plurality of matrix formatted bits;
bits within a row of the plurality of matrix formatted bits;
bits within a column of the plurality of matrix formatted bits;
the first plurality of parity bits; and
the second plurality of parity bits.
14. The apparatus of claim 11 , wherein:
the second encoder module being a multi-code encoder module to employ a first error correction code (ECC) to encode a first subset of the plurality of matrix formatted bits and employ a second ECC to encode a second subset of the plurality of matrix formatted bits.
15. The apparatus of claim 11 , wherein:
the apparatus being a operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
16. A method, comprising:
employing a matrix formatting module for:
partitioning a plurality of bits into a plurality of bit groups, such each of the plurality of bit groups respectively includes a consecutive subset of the plurality of bits; and
arranging the plurality of bit groups and at least one fill bit in accordance with a predetermined pattern to generate a plurality of matrix formatted bits that includes a predetermined plurality of bits such that at least one of the plurality of bit groups spans more than one matrix row of the plurality of matrix formatted bits;
employing an encoder module, communicatively coupled to the matrix formatting module, for at least one of:
encoding of bits within a plurality of rows of the plurality of matrix formatted bits thereby generating a first plurality of parity bits; and
encoding of bits within a plurality of columns of the plurality of matrix formatted bits thereby generating a second plurality of parity bits; and
arranging the plurality of matrix formatted bits and at least one of the first plurality of parity bits and the second plurality of parity bits thereby generating an output bit sequence.
17. The method of claim 16 , wherein:
the encoder module employs a Reed-Solomon (RS) code, a turbo code, a turbo trellis code modulation (TTCM) code, a LDPC (Low Density Parity Check) code, or a BCH (Bose and Ray-Chaudhuri, and Hocquenghem) code.
18. The method of claim 16 , further comprising interleaving at least one of:
the plurality of matrix formatted bits;
bits within a row of the plurality of matrix formatted bits;
bits within a column of the plurality of matrix formatted bits;
the first plurality of parity bits; and
the second plurality of parity bits.
19. The method of claim 16 , further comprising:
employing the encoder module for encoding at least one of the first plurality of parity bits and the second plurality of parity bits thereby generating a third plurality of parity bits; and
arranging the third plurality of parity bits in accordance with generating the output bit sequence.
20. The method of claim 16 , wherein:
the method being performed within a communication device; and
the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.