Methods of manufacturing charge trap type memory devices
View Patent ↗Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.
1. A method of manufacturing a charge trap type memory device, the method comprising:
forming a tunnel insulating layer on a substrate that has an isolation layer and a stepped active region;
forming a charge-trapping layer on the tunnel insulating layer;
forming an oxidation mask on the charge-trapping layer, the oxidation mask being configured to allow oxygen plasma ions to pass through to a portion of the charge-trapping layer over the isolation layer, wherein the oxidation mask is formed to have a portion over the isolation layer that is less thick than other portions of the oxidation mask to allow the oxygen plasma ions to pass therethrough and be implanted in the portion of the charge-trapping layer over the isolation layer;
converting the portion of the charge-trapping layer over the isolation layer into a charge-blocking pattern having a vertical side profile using an anisotropic oxidation process;
forming a blocking layer on the charge-trapping layer; and
forming gate electrodes on the blocking layer, the gate electrodes being electrically isolated from each other by a trench.
2. The method of claim 1 , wherein the charge-trapping layer comprises silicon nitride, and the charge-blocking pattern comprises silicon oxide or silicon oxynitride.
3. The method of claim 1 , further comprising etching the blocking layer after forming the gate electrodes.
4. The method of claim 1 , wherein the anisotropic oxidation process is performed in a plasma chamber to which a bias voltage is applied to direct plasma ions into the portion of the charge-trapping layer.
5. The method of claim 4 , further comprising forming the trench through the blocking layer and a conductive layer, which forms the gate electrodes, to expose a portion of the charge-trapping layer.
6. The method of claim 5 , wherein the anisotropic oxidation process is performed to implant plasma ions into the portion of the charge-trapping layer aligned with the trench.
7. The method of claim 1 , further comprising forming spacers on sidewalls of the gate electrodes.
8. The method of claim 7 , wherein:
the anisotropic oxidation process is performed in a plasma chamber to which a bias voltage is applied to direct plasma ions into the portion of the charge-trapping layer aligned with the trench; and
the spacers form an implantation mask that further narrows the portion of the charge-trapping layer into which the plasma ions are implanted to form the charge-blocking pattern.
9. A method of manufacturing a charge trap type memory device, the method comprising:
providing a substrate that has an isolation layer and a stepped active region;
forming a tunnel insulating layer on the substrate;
forming a charge-trapping layer on the tunnel insulating layer;
forming an oxidation mask on the charge-trapping layer, the oxidation mask being configured to allow oxygen plasma ions to pass through to a portion of the charge-trapping layer over the isolation layer;
converting the portion of the charge-trapping layer over the isolation layer into a charge-blocking pattern having a vertical side profile by an anisotropic oxidation process;
forming a blocking layer on the charge-trapping layer and the charge-blocking layer; and forming an electrode on the blocking layer,
wherein the oxidation mask is formed to have a portion over the isolation layer that is less thick than other portions of the oxidation mask to allow the oxygen plasma ions to pass therethrough and be implanted in the portion of the charge-trapping layer over the isolation layer.
10. A method of manufacturing a charge trap type memory device, the method comprising:
providing a substrate that has an isolation layer and a stepped active region;
forming a tunnel insulating layer on the substrate;
forming a charge-trapping layer on the tunnel insulating layer;
forming an oxidation mask on the charge-trapping layer, the oxidation mask being configured to allow oxygen plasma ions to pass through to a portion of the charge-trapping layer over the isolation layer;
converting the portion of the charge-trapping layer over the isolation layer into a charge-blocking pattern having a vertical side profile by an anisotropic oxidation process;
forming a blocking layer on the charge-trapping layer and the charge-blocking layer; and forming an electrode on the blocking layer;
wherein the oxidation mask is formed to have an opening that exposes the charge-trapping layer over the isolation layer.