IP Library Granted Patent US 8,514,035
Granted Patent B2
US 8,514,035 · App. 12/727,309 · Granted Aug 20, 2013

RF front-end with on-chip transmitter/receiver isolation using a gyrator

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Quick Facts
Patent No.
US 8,514,035
App. No.
12/727,309
Granted
Aug 20, 2013
Kind
B2
Abstract

An RF front-end with on-chip transmitter/receiver isolation using a gyrator is presented herein. The RF front end is configured to support full-duplex communication and includes a gyrator and a transformer. The gyrator includes two transistors that are configured to isolate the input of a low-noise amplifier (LNA) from the output of a power amplifier (PA). The gyrator is further configured to isolate the output of the PA from the input of the LNA. The gyrator is at least partially or fully capable of being integrated on silicon-based substrate.

Claims (41)

1. A radio frequency (RF) front-end configured to support full-duplex communication, comprising:

a gyrator comprising a first port coupled to an input of a low-noise amplifier (LNA) and a second port coupled to an output of a power amplifier (PA); and

a transformer comprising a primary winding coupled to an antenna and a secondary winding coupled between the first port and the second port,

wherein the gyrator is configured to isolate the output of the PA from the input of the LNA.

2. The RF front-end of claim 1 , wherein the primary winding and the secondary winding are inductively coupled.

3. The RF front-end of claim 1 , wherein the gyrator further comprises:

a first transistor comprising a source coupled to ground, a drain coupled to the first port, and a gate coupled to the second port; and

a second transistor comprising a source coupled to ground, a drain coupled to the second port, and a gate coupled to the first port.

4. The RF front-end of claim 3 , wherein the gyrator farther comprises an inverting amplifier coupled between the first port and the gate of the second transistor.

5. The RF front-end of claim 4 , wherein:

an input impedance of the first port is substantially equal to a reciprocal of a transconductance of the first transistor; and

an input impedance of the second port is substantially equal to a reciprocal of a negative transconductance of the second transistor.

6. The RF front-end of claim 3 , wherein the first transistor and the second transistor are metal oxide semiconductor field effect transistors (MOSFETs).

7. The RF front-end of claim 6 , wherein the first transistor and the second transistor are N-channel type MOSFETs.

8. The RF front-end of claim 3 , wherein a transconductance of the first transistor is substantially equal to a reciprocal of an equivalent resistance of the antenna as seen from the secondary winding.

9. The RF front-end of claim 3 , wherein a transconductance of the second transistor is substantially equal to a reciprocal of an equivalent resistance of the antenna as seen from the secondary winding.

10. A radio frequency (RF) front-end configured to support full-duplex communication, comprising:

a gyrator comprising:

a first transistor comprising a source coupled to ground, a drain coupled to a first port, and a gate coupled to a second port; and

a second transistor comprising a source coupled to ground, a drain coupled to the second port, and a gate coupled to the first port; and

a transformer comprising a primary winding coupled to an antenna and a secondary winding coupled between the first port and the second port of the gyrator,

wherein the gyrator is configured to isolate an input of a low noise amplifier (LNA), coupled to the first port, from the output of a power amplifier (PA), coupled to the second port.

11. The RF front-end of claim 10 , wherein the primary winding and secondary winding are inductively coupled.

12. The RF front-end of claim 10 , wherein the gyrator further comprises an inverting amplifier coupled between the first port and the gate of the second transistor.

13. The RF front-end of claim 12 , wherein:

an input impedance of the first port is substantially equal to a reciprocal of a transconductance of the first transistor; and

an input impedance of the second port is substantially equal to a reciprocal of a negative transconductance of the second transistor.

14. The RF front-end of claim 10 , wherein the first transistor and the second transistor are metal oxide semiconductor field effect transistors (MOSFETs).

15. The RF front-end of claim 14 , wherein the first transistor and the second transistor are N-channel type MOSFETs.

16. The RF front-end of claim 10 , wherein a transconductance of the first transistor is substantially equal to a reciprocal of an equivalent resistance of the antenna as seen from the secondary winding.

17. The RF front-end of claim 10 , wherein a transconductance of the second transistor is substantially equal to a reciprocal of an equivalent resistance of the antenna as seen from the secondary winding.

18. A radio frequency (RF) front-end configured to support full-duplex communication, comprising:

a first transistor comprising a source coupled to ground, a drain coupled to a first port, and a gate coupled to a second port; and

a second transistor comprising a source coupled to ground, a drain coupled to the second port, and a gate coupled to the first port,

wherein the first and second transistor are configured to isolate an input of a low noise amplifier (LNA), coupled to the first port, from the output of a power amplifier (PA), coupled to the second port.

19. The RF front-end of claim 18 , further comprising an antenna coupled between the first port and the second port.

20. The RF front-end of claim 18 , further comprising an inverting amplifier coupled between the first port and the gate of the second transistor.

21. A radio frequency (RF) front-end configured to support full-duplex communication, comprising:

a gyrator comprising a first port coupled to an input of a receiver and a second port coupled to an output of a transmitter; and

a transformer comprising a primary winding coupled to a signal transducer and a secondary winding coupled between the first port and the second port,

wherein the gyrator is configured to isolate the output of the transmitter from the input of the receiver.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER IN THE INCORRECT US PATENT NO. 8,876,094 PREVIOUSLY RECORDED ON REEL 047351 FRAME 0384. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 049248/0558 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF THE MERGER PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0910. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047351/0384 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0910 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2010
From: MIKHEMAR, MOHYEE; DARABI, HOOMAN
To: BROADCOM CORPORATION
Reel/Frame 024106/0581 →