Thin film transistor with polycrystalline semiconductor formed therein
View Patent ↗A thin film transistor (TFT) is provided which is capable of reducing leakage currents in a polycrystalline silicon TFT without causing an increase in manufacturing processes. Source/drain regions of an activated layer of the TFT to be formed in a circuit region and pixel region formed on a glass substrate of a liquid crystal display panel for a mobile phone is formed so that its boron impurity falls within a range of 2.5×10 18 /cm 3 to 5.5×10 18 /cm 3 and its impurity activation falls within a range of 1% to 7%.
1. A thin film transistor comprising:
a semiconductor layer formed on a substrate, said semiconductor layer comprising a polycrystalline semi-conductor;
a gate electrode formed on said semiconductor layer with a gate insulating film interposed between said semiconductor layer and said gate electrode; and
source/drain regions, doped with an impurity, formed in said semiconductor layer with said gate electrode being sandwiched between said source/drain regions,
wherein an impurity concentration is uniformly distributed over all of said source/drain regions within a range of 2.5×10 18 /cm 3 to 5.5×10 18 /cm 3 , all of the source and drain regions being defined as an entire region at least from each of both ends of said gate electrode to a corresponding one of a plurality of contact regions being in contact with source/drain wirings,
wherein contact resistance values at said contact regions each are greater than 40,000Ω and less than 360,000Ω, the contact resistance values resulting from contact of said source/drain regions with said source/drain wirings, and
wherein sheet resistance values of said source/drain regions each are greater than 1.5×10 5 Ω/square and less than 5 ×10 5 Ω/square.
2. The thin film transistor according to claim 1 , wherein said semiconductor layer is a polycrystalline silicon film.
3. The thin film transistor according to claim 1 , wherein an activation rate of said impurity is uniformly distributed over all of said source/drain regions within a range of 1% to 3%.
4. The thin film transistor according to claim 1 , wherein boron or phosphorous is used as said impurity to be doped into said source/drain regions.
5. The thin film transistor according to claim 1 , wherein a plurality of gate electrodes is arranged in parallel and all of said plurality of gate electrodes are connected to a common gate wiring.
6. A liquid crystal display panel comprising a thin film transistor of claim 1 .
7. An electronic device comprising:
a thin film transistor, said thin film transistor comprising:
a polycrystalline semiconductor layer formed on a substrate;
a gate electrode formed on said polycrystalline semiconductor layer with a gate insulating film interposed between said polycrystalline semiconductor layer and said gate electrode; and
source/drain regions, doped with an impurity, formed in said polycrystalline semiconductor layer with said gate electrode being sandwiched between said source/drain regions,
wherein an impurity concentration is uniformly distributed over all of said source/drain regions within a range of 2.5×10 18 /cm 3 to 5.5×10 18 /cm 3 , all of the source and drain regions being defined as an entire region at least from each of both ends of said gate electrode to a corresponding one of a plurality of contact regions being in contact with source/drain wirings,
wherein contact resistance values at said contact regions each are greater than 40,000Ω and less than 360,000Ω, the contact resistance values resulting from contact of said source/drain regions with said source/drain wirings, and
wherein sheet resistance values of said source/drain regions each are greater than 1.5×10 5 Ω/square and less than 5 ×10 5 Ω/square.