IP Library Granted Patent US 8,661,314
Granted Patent B2
US 8,661,314 · App. 12/728,059 · Granted Feb 25, 2014

Method and apparatus for calculating frame check sequence

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Quick Facts
Patent No.
US 8,661,314
App. No.
12/728,059
Granted
Feb 25, 2014
Kind
B2
Abstract

One embodiment provides a system for calculating a checksum for a packet. During operation, the system receives a packet, pads the received packet with a number of bits having predetermined values, and calculates an initial checksum value for the padded packet. Subsequently, the system calculates a final checksum for the original packet by reversing the initial checksum value using the padded bits with predetermined values.

Claims (41)

1. An apparatus, comprising:

a receiving mechanism configured to receive a first packet;

a padding mechanism configured to pad the first received packet with a number of bits having predetermined values to provide a second packet;

a first logic element configured to calculate an initial checksum value corresponding to the second packet; and

a second logic element configured to shift the initial checksum value by a number of shifts equal to the number of padded bits to rewind the initial checksum value and to provide a final checksum value corresponding to the first packet.

2. The apparatus of claim 1 , wherein the predetermined values are all zeros.

3. The apparatus of claim 1 , wherein the initial checksum value is a cyclic redundancy check (CRC) value of the second packet, and

wherein the final checksum value is a CRC value of the first packet.

4. The apparatus of claim 1 , wherein the first logic element is configured to calculate the initial checksum value based on a first polynomial.

5. The apparatus of claim 4 , wherein the second logic element is further configured to calculate the final checksum value by reversing the initial checksum value calculation based on a second polynomial, and

wherein the second polynomial is an invert of the first polynomial.

6. The apparatus of claim 1 , wherein the second logic element is further configured to calculate the final checksum value utilizing a plurality of processing stages, and wherein an initial stage of the plurality of processing stages is set based on the initial checksum value.

7. The apparatus of claim 1 , wherein the second packet has a length that is a multiple of a data-path width of the first logic element.

8. The apparatus of claim 7 , wherein the first logic element is further configured to calculate the initial checksum value by processing bits of the initial checksum value in a parallel manner according to the data-path width.

9. The apparatus of claim 1 , wherein the first packet is an Ethernet packet.

10. A system for calculating a checksum value for a first packet, comprising:

a padding mechanism configured to pad the first packet with a number of zeros to provide a second packet;

a forward-checksum calculator having a predetermined data-path width configured to calculate an initial checksum value corresponding to the second packet in a parallel manner according to the predetermined data-path width; and

a reverse-checksum calculator configured to shift the initial checksum value by a number of shifts equal to the number of padded zeros to calculate a final checksum value corresponding to the first packet.

11. The system of claim 10 , wherein the forward-checksum calculator is configured to perform the initial checksum value calculation based on a first polynomial.

12. The system of claim 11 , wherein the initial checksum value is a cyclic redundancy check (CRC) value of the second packet, and

wherein the final checksum value is a CRC value of the first packet.

13. The system of claim 11 , wherein the reverse-checksum calculator is configured to calculate the final checksum value by reversing the checksum value calculation based on a second polynomial, and

wherein the second polynomial is an invert of the first polynomial.

14. The system of claim 10 , wherein the second packet has a length that is a multiple of the predetermined data-path width.

15. The system of claim 10 , wherein the first packet is an Ethernet packet.

16. In a cyclic redundancy code (CRC) checking logic device, a method comprising:

receiving a first packet of data having a first bit length;

comparing the first bit length to a second bit length;

calculating a first CRC value corresponding to the first packet if the first bit length and the second bit length are multiples of one another, and otherwise;

padding the first packet with a number of zero bits such that the first bit length and the second bit length are multiples of one another, to provide a second packet,

calculating a second CRC value corresponding to the second packet, and

shifting the second CRC value of the second packet by a number of shifts equal to the number of zero bits to calculate the first CRC value.

17. The method of claim 16 , wherein comparing the first bit length to the second bit length is performed by a forward checksum calculator having a predetermined data-path width, and

wherein the second bit length is equal to the predetermined data-path width.

18. The method of claim 16 , wherein calculating the second CRC value comprises:

calculating the second CRC value based on a first polynomial.

19. The method of claim 18 , wherein shifting the second CRC value comprises:

shifting the second CRC value by performing a calculation on the second CRC value utilizing a second polynomial to determine the first CRC value, the second polynomial being an invert of the first polynomial.

20. The method of claim 17 , wherein calculating the first CRC value comprises:

calculating the first CRC value by processing bits of the first CRC value of the packet in a parallel manner according to the predetermined data-path width.

Assignments (5)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2010
From: HIRTH, RYAN E.
To: TEKNOVUS, INC.
Reel/Frame 025773/0775 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2010
From: TEKNOVUS, INC.
To: BROADCOM CORPORATION
Reel/Frame 024864/0231 →