Method and apparatus for adapting a variable impedance network

1. A tunable capacitor, comprising:

a decoder for generating a plurality of control signals;

an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches;

wherein the plurality of switches are controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors,

wherein the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors,

wherein each of the switches are adapted to have a parasitic resistance which results in the non-uniform Q factors of the array of tunable switched capacitors,

wherein at least one of the switches comprises one of a plurality of semiconductor switches or a plurality of micro-electro-mechanical systems (MEMS) switches, and

wherein a scaling factor of the plurality of semiconductor switches or the plurality of MEMS switches results in the non-uniform Q factors of the array of tunable switched capacitors.

2. The tunable capacitor of claim 1 , wherein the scaling factor comprises combining switches in parallel or widening a conducting channel of such switches.

3. The tunable capacitor of claim 1 , wherein at least a portion of the array of tunable switched capacitors is contained on a die.

4. The tunable capacitor of claim 1 , wherein the coupled fixed capacitor is located externally to a die, wherein one of the plurality of switches is coupled to a first external port of the die, wherein a portion of the array of tunable switched capacitors is coupled to a second external port of the die, and wherein the coupled fixed capacitor is couplable to the array of tunable switched capacitors by way of the first and second external ports.

5. The tunable capacitor of claim 1 , wherein the plurality of fixed capacitors comprise capacitive values conforming to a binary sequence.

6. The tunable capacitor of claim 1 , wherein the plurality of fixed capacitors comprise capacitive values conforming to a non-binary sequence.

7. The tunable capacitor of claim 1 , wherein the decoder is adapted to receive data over a serial port to generate the plurality of control signals.

8. The tunable capacitor of claim 1 , wherein one of the plurality of fixed capacitors is coupled to the array of tunable switched capacitors to reduce an aggregate parasitic capacitance of the array of tunable switched capacitors.

9. The tunable capacitor of claim 8 , wherein one end of the coupled fixed capacitor is coupled to a first external port of a die, wherein a portion of the array of tunable switched capacitors is coupled to a second external port of the die, and wherein the coupled fixed capacitor is couplable to the array of tunable switched capacitors by way of the first and second external ports.

10. The tunable capacitor of claim 1 , wherein the tunable capacitor is utilized as a plurality of the tunable capacitors in a variable matching network.

11. The tunable capacitor of claim 10 , wherein the variable matching network comprises a plurality of ports to support a plurality of matching network topologies comprising one of a “Tee” topology, a “Pi” topology, an “L” topology, or a combination thereof.

12. The tunable capacitor of claim 10 , wherein the variable matching network is configurable as a high band or low band matching network.

13. A device, comprising first and second variable capacitors within a single die with each end of said first and second variable capacitors having an accessible external port, wherein the first and second variable capacitors are adapted to be configured as a Tee, Pi or L circuit topology.

14. The device of claim 13 , wherein a plurality of the devices are utilized in a corresponding plurality of RF paths.

15. The device of claim 14 , wherein the plurality RF paths correspond to at least one of high or low band RF paths.

16. The device of claim 15 , wherein the high or low band RF paths are switchable among a plurality of ports of the single die.

17. The device of claim 13 , wherein the first and second variable capacitors comprise an array of tunable switched capacitors adapted to have non-uniform quality (Q) factors.

18. The device of claim 17 , wherein the array of tunable switched capacitors comprises a plurality of fixed capacitors coupled to a plurality of switches.

19. The device of claim 18 , wherein at least one of the switches comprises one of a plurality of semiconductor switches or a plurality of micro-electro-mechanical systems (MEMS) switches.

20. The device of claim 18 , wherein the plurality of switches are scaled to reduce a size of the single die thereby providing the non-uniform Q factors in the array of tunable switched capacitors.

21. A tunable capacitor on a die, comprising:

a decoder for generating a plurality of control signals;

an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches;

wherein the plurality of switches are controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors;

wherein one of the plurality of fixed capacitors is coupled to the array to reduce an aggregate parasitic capacitance of the array of tunable switched capacitors,

wherein the array of tunable switched capacitors is adapted to have uniform quality (Q) factors,

wherein one end of the coupled fixed capacitor is coupled to a first external port of the die,

wherein a portion of the array of tunable switched capacitors is coupled to a second external port of the die, and

wherein the coupled fixed capacitor is couplable to the array of tunable switched capacitors by way of the first and second external ports.

22. A tunable capacitor on a die, comprising:

a decoder for generating a plurality of control signals;

an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches;

wherein the plurality of switches are controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors;

wherein one of the plurality of fixed capacitors is coupled to the array to reduce an aggregate parasitic capacitance of the array of tunable switched capacitors,

wherein the array of tunable switched capacitors is adapted to have uniform quality (Q) factors,

wherein the coupled fixed capacitor is located externally to the die,

wherein one of the plurality of switches is coupled to a first external port of the die,

wherein a portion of the array of tunable switched capacitors is coupled to a second external port of the die, and

wherein the coupled fixed capacitor is couplable to the array of tunable switched capacitors by way of the first and second external ports.

23. A method, comprising:

causing an array of tunable switched reactive elements to adapt to a variable load impedance; and

configuring the array of tunable switched reactive elements to have non-uniform quality (Q) factors,

wherein the array of tunable switched reactive elements comprises one of one or more fixed capacitors coupled to one or more switches, one or more fixed inductors coupled to one or more switches, or combinations thereof,

wherein at least one of the switches comprises one of a plurality of semiconductor switches or a plurality of micro-electro-mechanical systems (MEMS) switches, and

wherein a scaling factor of the plurality of semiconductor switches or the plurality of MEMS switches results in the non-uniform Q factors of the array of tunable switched reactive elements.