Gate drive device for a liquid crystal display including multiple stages of shift register units

1. A gate drive device for a liquid crystal display, including multiple stages of shift register units and a plurality of clock signal lines, each of said plurality of clock signal lines being connected to the multiple stages of shift register units, to enable the multiple stages of shift register units to generate a gate drive signal, each stage of shift register unit including a signal output terminal,

wherein a first discharge circuit modular is connected between the signal output terminal for the i-th stage of shift register unit and the signal output terminal for the (i+1)-th stage of shift register unit, said first discharge circuit modular is used for causing the charges of a high level signal outputted from the signal output terminal for the i-th stage of shift register unit to be discharged to the signal output terminal for the (i+1)-th stage of shift register unit,

wherein 1≦i≦the number of the stages of shift register units−1;

wherein the device further comprises a second discharge circuit modular,

wherein a first clock signal line comprises a first clock signal primary line and a first clock signal secondary line, a second clock signal line comprises a the second clock signal primary line and a second clock signal secondary line; said first clock signal primary line and the first clock signal secondary line are connected in parallel; said second clock signal primary line and a second clock signal secondary line are connected in parallel; and

wherein the second discharge circuit modular is connected between the first clock signal line and the second clock signal line, the second discharge circuit modular is used for causing the charges of a high level signal on the first clock signal primary line to be discharged to the second clock signal primary line, or for causing the charges of a high level signal in the second clock signal primary line to be discharged to the first clock signal primary line; and

wherein the second discharge circuit modular comprises a third thin film transistor and a fourth thin film transistor;

for each of the odd number stages of shift register unit of the multiple stages of shift register units, both of the gate and drain of the third thin film transistor are connected to the first clock signal primary line, the drain of the fourth thin film transistor is connected to the source of the third thin film transistor, the source of the fourth thin film transistor is connected to the second clock signal primary line, the gate of the fourth thin film transistor is connected to the second clock signal secondary line, and the gate of the second thin film transistor is connected to the second clock signal secondary line; and

for each of the even number stages of shift register unit of the multiple stages of shift register units, both of the gate and drain of the third thin film transistor are connected to the second clock signal primary line, the drain of the fourth thin film transistor is connected to the source of the third thin film transistor, the source of the fourth thin film transistor is connected to the first clock signal primary line, the gate of the fourth thin film transistor is connected to the first clock signal secondary line, and the gate of the second thin film transistor is connected to the first clock signal secondary line.

2. The device as claimed in claim 1 , wherein said first discharge circuit modular comprises a first thin film transistor and a second thin film transistor;

both of the gate and the drain of the first thin film transistor are connected to the signal output terminal for the i-th stage of shift register unit; and

the drain of the second thin film transistor is connected to the source of the first thin film transistor, the source of the second thin film transistor is connected to the signal output terminal for the (i+1)-th stage of the shift register unit, and the gate of the second thin film transistor is connected to one of the plurality of the clock signal lines.

3. The device as claimed in claim 2 , wherein said plurality of the clock signal lines comprise said first clock signal line and said second clock signal line, the clock signal inputted in the first clock signal line and the clock signal inputted in the second clock signal line are signals which are phase-reversed with respect to each other;

for each of the odd number stages of shift register unit of the multiple stages of shift register units, the gate of the second thin film transistor is connected to the second clock signal line; and

for each of the even number stages of shift register unit of the multiple stages of shift register units, the gate of the second thin film transistor is connected to the first clock signal line.

4. A gate drive device for a liquid crystal display, comprising multiple stages of shift register units and a plurality of clock signal lines, each of said plurality of clock signal lines being connected to the multiple stages of shift register units to enable the multiple stages of shift register units to generate a gate drive signal,

wherein each of said plurality of clock signal lines comprises a clock signal primary line and a clock signal secondary line which are connected in parallel; and

wherein a discharge circuit modular is connected between two clock signal lines among said plurality of clock signal lines, and the discharge circuit modular is used for causing the charges of a high level signal on the clock signal primary line of one of the two clock signal lines to be discharged to the clock signal primary line of the other of the two clock signal lines,

wherein the discharge circuit modular comprises a first thin film transistor and a second thin film transistor; and

wherein both of the gate and drain of the first thin film transistor are connected to the clock signal primary line of one of the two clock signal lines, the drain of the second thin film transistor is connected to the source of the first thin film transistor, the source of the second thin film transistor is connected to the clock signal primary line of the other of the two clock signal lines, and the gate of the second thin film transistor is connected to the clock signal secondary line of the other of the two clock signal lines.

5. The device as claimed in claim 4 , wherein said, two clock signal lines comprise a first clock signal line and a second clock signal line;

said first clock signal line comprises a first clock signal primary line and a first clock signal secondary line, and said second clock signal line comprises a the second clock signal primary line and a second clock signal secondary line;

said first clock signal primary line and the first clock signal secondary line are connected in parallel, and said second clock signal primary line and a second clock signal secondary line are connected in parallel;

for each of the odd number stages of shift register unit of the multiple stages of shift register units, both of the gate and drain of the first thin film transistor are connected to the first clock signal primary line, the drain of the second thin film transistor is connected to the source of the first thin film transistor, the source of the second thin film transistor is connected to the second clock signal primary line, and the gate of the second thin film transistor is connected to the second clock signal secondary line; and

for each of even number stages of shift register unit of the multiple stages of shift register units, both of the gate and drain of the first thin film transistor are connected to the second clock signal primary line, the drain of the second thin film transistor is connected to the source of the first thin film transistor, the source of the second thin film transistor is connected to the first clock signal primary line, and the gate of the second thin film transistor is connected to the first clock signal secondary line.