IP Library Patent Application 12730609
Patent Application
App. No. 12/730,609

WAFER BUMPING USING PRINTED UNDER BUMP METALIZATION

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Quick Facts
Patent No.
US None
App. No.
12/730,609
Abstract

Methods, systems, and apparatuses for printing under bump metallization (UBM) features on chips/wafers are provided. A wafer is received that has a surface defined by a plurality of integrated circuit regions. Each integrated circuit region has a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer. A plurality of UBM features are formed on the surface of the wafer in the form of an ink such that each UBM feature is formed electrically coupled with a corresponding terminal of the plurality of terminals. An ink jet printer may be used to print the ink in the form of the UBM feature. A UBM feature may be formed directly on a corresponding terminal, or on routing that is coupled to the corresponding terminal. A bump interconnect may be formed on the UBM feature.

Claims (57)

1 . A method, comprising:

receiving a wafer having a surface defined by a plurality of integrated circuit regions, each integrated circuit region having a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer; and

printing a plurality of under bump metallization (UBM) features in the form of an ink on the surface of the wafer such that each UBM feature is formed electrically coupled with a corresponding terminal of the plurality of terminals.

2 . The method of claim 1 , wherein said printing comprises:

printing a UBM feature in the form of an ink directly on at least one terminal of the plurality of terminals.

3 . The method of claim 1 , further comprising:

forming a plurality of routing interconnects on the surface of the wafer such that each routing interconnect has a first portion in contact with a respective terminal of the plurality of terminals and has a second portion that extends over the passivation layer;

wherein said printing comprises

printing a plurality of UBM features in the form of an ink on the plurality of routing interconnects such that each UBM feature is formed on the second portion of a respective routing interconnect of the plurality of routing interconnects.

4 . The method of claim 1 , further comprising:

forming a plurality of bump interconnects on the plurality of UBM features.

5 . The method of claim 4 , wherein said forming comprises:

printing the plurality of bump interconnects in the form of an ink on the plurality of UBM features

6 . The method of claim 1 , wherein the ink includes a metal paste, wherein said printing comprises:

printing the metal paste on the surface of the wafer to form the plurality of UBM features.

7 . The method of claim 1 , wherein said printing comprises:

ink jet printing the plurality of UBM features on the surface of the wafer.

8 . The method of claim 1 , wherein said printing comprises:

printing a first ink on a first region of the surface of the wafer to form a first UBM feature electrically coupled to a first terminal; and

printing a second ink on a second region of the surface of the wafer to form a second UBM feature electrically coupled to a second terminal;

wherein the second ink is different from the first ink.

9 . The method of claim 1 , wherein said printing comprises:

printing a plurality of layers of ink to form at least one of the UBM features.

10 . The method of claim 9 , wherein said printing comprises:

printing a first ink on the surface of the wafer to form a first layer of the plurality of layers of ink of a first UBM feature; and

printing a second ink on the first layer to form a second layer of the plurality of layers of ink of the first UBM feature;

wherein the second ink is different from the first ink.

11 . The method of claim 1 , further comprising:

singulating the wafer to form a plurality of integrated circuit packages that each include at least one integrated circuit region of the plurality of integrated circuit regions.

12 . An integrated circuit (IC) package, comprising:

an integrated circuit die having a plurality of terminals on a surface of the integrated circuit die;

a passivation layer on the surface of the integrated circuit die having a plurality of openings that provide access to the plurality of terminals; and

a plurality of under bump metallization (UBM) features printed on the integrated circuit die, each UBM feature being electrically coupled to a corresponding terminal of the plurality of terminals, and each UBM feature comprising a solidified ink.

13 . The IC package of claim 12 , wherein at least one UBM feature is formed directly on a corresponding terminal of the plurality of terminals.

14 . The IC package of claim 12 , further comprising:

a plurality of routing interconnects each having a first portion and a second portion, the first portion of each routing interconnect being in contact with a respective terminal of the plurality of terminals though a respective opening in the passivation layer and the second portion of each routing interconnect extending over the passivation layer;

wherein each UBM feature is printed on the second portion of a respective routing interconnect of the plurality of routing interconnects.

15 . The IC package of claim 12 , further comprising:

a plurality of bump interconnects printed on the plurality of UBM features.

16 . The IC package of claim 15 , wherein the plurality of bump interconnects is arranged in an array of bump interconnects.

17 . The IC package of claim 12 , wherein the ink includes a metal paste.

18 . The IC package of claim 17 , wherein the metal paste is a nanopaste.

19 . The IC package of claim 18 , wherein the metal paste includes at least one of silver or copper.

20 . The IC package of claim 12 , wherein a first UBM feature of the plurality of UBM features is printed on a first region of the surface of the integrated circuit die using a first ink, the first UBM feature being electrically coupled to a first terminal;

wherein a second UBM feature of the plurality of UBM features is printed on a second region of the surface of the integrated circuit die using a second ink, the second UBM feature being electrically coupled to a second terminal; and

wherein the second ink is different from the first ink.

21 . The IC package of claim 12 , wherein at least one UBM feature comprises a stack of layers of solidified ink.

22 . The IC package of claim 21 , wherein a first UBM feature of the plurality of UBM features includes a first UBM layer formed of a first ink printed on the surface of the wafer and a second UBM layer formed of a second ink printed on the first UBM layer;

wherein the second ink is different from the first ink.

23 . A system for processing a wafer to form integrated circuit (IC) packages, comprising:

an ink jet printer configured to print a plurality of under bump metallization (UBM) features on the surface of a wafer in the form of an ink, the wafer having a surface defined by a plurality of integrated circuit regions, each integrated circuit region having a passivation layer and a plurality of terminals on the surface of the wafer accessible through openings in the passivation layer.

24 . The system of claim 23 , further comprising:

a solder bump applicator configured to form a plurality of bump interconnects on the plurality of UBM features such that each bump interconnect of the plurality of bump interconnects is formed on a respective UBM feature.

25 . The system of claim 23 , wherein the ink jet printer is configured to print using a metal paste as the ink.

26 . The system of claim 25 , wherein the ink jet printer is configured to print using a nanopaste as the metal paste.

27 . The system of claim 25 , wherein the metal paste includes at least one of silver or copper.

28 . The system of claim 23 , wherein the ink jet printer includes a plurality of print heads configured to spray ink.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2010
From: HU, KUNZHONG (KEVIN); LAW, EDWARD
To: BROADCOM CORPORATION
Reel/Frame 024200/0411 →