Vertical alignment mode liquid crystal display and method of manufacturing the same

1. A vertical alignment liquid crystal display comprising:

a first substrate;

a second substrate disposed opposite the first substrate; and

a liquid crystal layer disposed between the first substrate and the second substrate, wherein

the first substrate comprises:

a first insulation substrate;

a gate insulating layer disposed on the first insulating substrate;

a first semiconductor disposed on the gate insulating layer;

a first data line disposed on the first semiconductor;

a second semiconductor disposed on the gate insulating layer;

a second data line disposed on the second semiconductor;

a passivation layer disposed on the first data line and the second data line;

a first pixel electrode disposed on the passivation layer;

a second pixel electrode disposed on the passivation layer; and

a first alignment layer disposed on the first pixel electrode and the second pixel electrode,

the second substrate comprises:

a second insulation substrate;

a patterned conductive layer disposed on only a portion of the second insulation substrate which is above the first data line and the second data line; and

a second alignment layer disposed on the patterned conductive layer,

the liquid crystal layer includes vertically aligned liquid crystal molecules,

the first pixel electrode and the second pixel electrode are disposed in a same layer on the first insulation substrate, and

the first pixel electrode and the second pixel electrode each comprise:

a projection portion;

a longitudinal stem portion;

a transverse stem portion; and

branch portions extending from the longitudinal stem and the transverse stem, the branch portions forming about a 45 degree angle with both the longitudinal stem and the transverse stem.

2. The vertical alignment liquid crystal display of claim 1 , further comprising:

a first storage electrode disposed on the first insulation substrate under the gate insulation layer; and

a second storage electrode disposed on the first insulation substrate under the gate insulation layer.

3. The vertical alignment liquid crystal display of claim 2 , wherein

the first pixel electrode is disposed on the passivation layer above a portion of the first storage electrode, and

the second pixel electrode is disposed on the passivation layer above a portion of the second storage electrode.

4. The vertical alignment liquid crystal display of claim 2 , further comprising:

a first ohmic contact disposed on the first semiconductor; and

a second ohmic contact disposed on the second semiconductor, wherein

the first storage electrode is disposed on the first ohmic contact, and

the second storage electrode is disposed on the second ohmic contact.

5. The vertical alignment liquid crystal display of claim 2 , further comprising a storage extension part connected to the first storage electrode and the second storage electrode and disposed on the first substrate under the projection portions of the first pixel electrode and the second pixel electrode.

6. The vertical alignment liquid crystal display of claim 5 , further comprising:

a first drain electrode extension disposed on the gate insulating layer between the projection portion of the first pixel electrode and the storage extension part; and

a second drain electrode extension disposed on the gate insulating layer between the projection portion of the second pixel electrode and the storage extension part, wherein

an area of each of the first drain electrode extension and the second drain electrode extension is greater than an area of each of a first drain electrode and a second drain electrode, respectively.

7. The vertical alignment liquid crystal display of claim 1 , further comprising:

a light blocking member disposed on the patterned conductive layer.

8. The vertical alignment liquid crystal display of claim 7 , wherein

the light blocking member overlaps a portion of the first data line and the second data line.

9. The vertical alignment liquid crystal display of claim 7 , wherein at least the light blocking member includes a dual-layer structure.

10. The vertical alignment liquid crystal display of claim 1 , further comprising:

a color filter disposed on a portion of a light blocking member.

11. The vertical alignment liquid crystal display of claim 10 , further comprising an overcoat disposed on the color filter.

12. The vertical alignment liquid crystal display of claim 1 , wherein

the branch portions of the first pixel electrode are interdigitated with the branch portions of the second pixel electrode.

13. The vertical alignment liquid crystal display of claim 12 , wherein,

upper branch portions of the branch portions of both the first pixel electrode and the second pixel electrode are parallel to each other,

lower branch portions of the branch portions of both the first pixel electrode and the second pixel electrode are parallel to each other, and

the upper branch portions form about a 90 degree angle with the lower branch portions.

14. The vertical alignment liquid crystal display of claim 1 , wherein at least one of the patterned conductive layer is electrically floated.

15. A method of manufacturing a vertical alignment liquid crystal display, the method comprising:

forming a first substrate;

forming a second substrate opposite to the first substrate;

interposing a liquid crystal layer between the first substrate and the second substrate;

forming a first insulation substrate on the first substrate;

forming a gate insulating layer on the first insulating substrate;

forming a first semiconductor and a second semiconductor on the gate insulating layer;

forming a first data line on the first semiconductor;

forming a second data line on the second semiconductor;

forming a passivation layer on the first data line and the second data line;

forming a first pixel electrode and a second pixel electrode on the passivation layer;

forming a first alignment layer on the first pixel electrode and the second pixel electrode;

forming a second insulation substrate on the second substrate;

forming a first patterned conductive layer on only a portion of the second insulation substrate which is above the first pixel electrode and the first data line;

forming a second patterned conductive layer on only a portion of the second insulation substrate which is above the second pixel electrode and the second data line;

forming a second alignment layer on the first patterned conductive layer and the second patterned conductive layer, wherein

the liquid crystal layer includes vertically aligned liquid crystal molecules,

the first pixel electrode and the second pixel electrode are disposed in a same layer on the first insulation substrate, and

the first pixel electrode and the second pixel electrode each comprise:

a projection portion;

a longitudinal stem portion;

a transverse stem portion; and

branch portions extending from the longitudinal stem and the transverse stem, the branch portions forming about a 45 degree angle with both the longitudinal stem and the transverse stem, wherein the branch portions of the first pixel electrode are interdigitated with the branch portions of the second pixel electrode.

16. The method of claim 15 , further comprising:

forming a first storage electrode on the first insulation substrate under the gate insulation layer;

forming a second storage electrode on the first insulation substrate under the gate insulation layer;

forming a first ohmic contact on the first semiconductor; and

forming a second ohmic contact on the second semiconductor, wherein

the first storage electrode is disposed on the first ohmic contact, and

the second storage electrode is disposed on the second ohmic contact,

the first pixel electrode is disposed on the passivation layer above a portion of the first storage electrode, and

the second pixel electrode is disposed on the passivation layer above a portion of the second storage electrode.

17. The method of claim 16 , further comprising:

forming a storage extension part connected to the first storage electrode and the second storage electrode and disposed on the first substrate under the projection portions of the first pixel electrode and the second pixel electrode;

forming a first drain electrode extension on the gate insulating layer between the projection portion of the first pixel electrode and the storage extension part; and

forming a second drain electrode extension on the gate insulating layer between the projection portion of the second pixel electrode and the storage extension part, wherein

an area of each of the first drain electrode extension and the second drain electrode extension is greater than an area of each of a first drain electrode and a second drain electrode, respectively.

18. The method of claim 15 , further comprising:

forming a first light blocking member on the first patterned conductive layer; and

forming a second light blocking member on the second patterned conductive layer, wherein

the first light blocking member overlaps the first data line and a portion of the first pixel electrode,

the second light blocking member overlaps the second data line and a portion of the second pixel electrode, and

at least one of the first light blocking member and the second light blocking member includes a dual-layer structure.

19. The method of claim 15 , further comprising:

forming a first color filter on a first portion of a first light blocking member;

forming a second color filter on a second portion of a second light blocking member; and

forming an overcoat on the first color filter and the second color filter.

20. The method of claim 15 , wherein

upper branch portions of the branch portions of both the first pixel electrode and the second pixel electrode are parallel to each other,

lower branch portions of the branch portions of both the first pixel electrode and the second pixel electrode are parallel to each other, and

the upper branch portions form about a 90 degree angle with the lower branch portions.

21. The method of claim 15 , wherein at least one of the first patterned conductive layer and the second patterned conductive layer is electrically floated.