Method and apparatus for reconfigurable at-speed test clock generator

1. An apparatus comprising:

a PLL included in an integrated circuit for generating a first clock signal including pulses at a first frequency; and

a controller for providing said first clock signal to a circuit within said integrated circuit during a first mode of operation, and for providing a second clock signal at a second frequency lower than said first frequency to said circuit within said integrated circuit during a second mode of operation and for providing a third clock signal having a first portion comprising a plurality of said pulses of said first clock signal at said first frequency and a second portion, wherein the second portion includes none of said pulses of said first clock signal and has a duration greater than a pulse width of said first clock signal.

2. The apparatus of claim 1 , wherein a waveform of the third clock signal corresponds to a bit pattern stored in a register.

3. The apparatus of claim 1 wherein the third clock signal is generated in response to data associated with a reconfigurable number of programmable at-speed phase-locked loop clock pulses is stored in a configurable register.

4. The apparatus of claim 3 , wherein the data associated with a reconfigurable number of programmable at-speed phase-locked loop clock pulses is stored in a dead cycle configurable load register.

5. The apparatus of claim 4 , wherein the dead cycle configurable load register is utilized for multi-cycle paths and related clocks.

6. The apparatus of claim 4 , wherein the dead cycle configurable load register is loaded with a scan chain.

7. The apparatus of claim 4 , wherein the dead cycle configurable load register is controlled with input pins.

8. An integrated circuit comprising:

a first register;

a second register;

a third register; and

a controller for enabling transfer of data in parallel from said first register to said second register responsive to a first clock signal at a first frequency during a first mode of operation, and for enabling transfer of data in series from said first register to said second register responsive to a second clock signal at a second frequency during a second mode of operation, and for enabling transfer of data in parallel between said first register and said second register responsive to a third clock signal having a waveform corresponding to a bit pattern stored in said third register.

9. The integrated circuit of claim 8 , wherein the bit pattern corresponds to data associated with a reconfigurable number of programmable at-speed phase-locked loop clock pulses is stored in a configurable register.

10. The integrated circuit of claim 9 , wherein the data associated with a reconfigurable number of programmable at-speed phase-locked loop clock pulses is stored in a dead cycle configurable load register.

11. The integrated circuit of claim 10 , wherein the dead cycle configurable load register is utilized for multi-cycle paths and related clocks.

12. The integrated circuit of claim 10 , wherein the dead cycle configurable load register is loaded with a separate scan chain.

13. The integrated circuit of claim 10 , wherein the dead cycle configurable load register is controlled with primary input pins.

14. A method comprising the steps of:

receiving a bit pattern corresponding to a number of clock cycles, wherein said bit pattern represents a clock signal waveform;

transferring data in parallel between a first register and a second register in a first mode of operation;

transferring data in series between said first and said second register in a second mode of operation;

transferring data in parallel between said first register and said second register for said number of clock cycles in said second mode of operation in response to a clock signal corresponding to said clock signal waveform; and

transferring data in series between said first register and said second register in said second mode of operation.

15. The method of claim 14 , wherein the bit pattern is stored in one or more configurable registers.

16. The method of claim 14 , wherein the bit pattern is stored in a dead cycle configurable load register.

17. The method of claim 16 , wherein the dead cycle configurable load register is utilized for multi-cycle paths and related clocks.

18. The method of claim 16 , wherein the dead cycle configurable load register is loaded with a separate scan chain.

19. The method of claim 16 , wherein the dead cycle configurable load register is controlled with primary input pins.

20. A method of testing an integrated circuit comprising the steps of:

receiving a bit pattern corresponding to a number of clock cycles, wherein said bit pattern represents a clock signal waveform;

storing said bit pattern in a first register;

transferring data in parallel between a second register and a third register;

receiving a command signal;

transferring data in series between said second register and said third register in response to said command signal;

stopping said serial transfer of data between the second register and the third register;

transferring data in parallel between the second register and the third register for said number of clock cycles in response to a clock signal corresponding to said clock signal waveform; and

resuming said serial transfer of data between the second register and the third register.

21. The method of claim 20 , wherein the bit pattern is stored in a configurable register.

22. The method of claim 20 , wherein the bit pattern is stored in a dead cycle configurable load register.

23. The method of claim 22 , wherein the dead cycle configurable load register is utilized for multi-cycle paths and related clocks.

24. The method of claim 22 , wherein the dead cycle configurable load register is loaded with a separate scan chain.

25. The method of claim 22 , wherein the dead cycle configurable load register is controlled with primary input pins.