Compact and accurate analog memory for CMOS imaging pixel detectors
View Patent ↗An analog memory circuit, i.e. a sample and hold circuit, wherein the source and the gate of the switching transistor is maintained at a same potential prior and after the sampling process using a transistor circuitry. The analog memory circuit comprises a memory capacitor ( 102 ) connected at a first end to a first port ( 104 ), which is connected a reference potential ( 106 ). A drain of a first transistor ( 108 ) —switch transistor—is connected to a second end of the memory capacitor ( 102 ). A source of the first transistor ( 108 ) is connected to a second port ( 110 ), which is connected to circuitry ( 112 ) for providing an input signal for storage in the memory capacitor ( 102 ), and a gate of the first transistor ( 108 ) is connected to a third port ( 114 ), which is connected to a first current sink ( 116 ). A source of a second transistor ( 118 ) is connected to the source of the first transistor ( 108 ) and a drain of the second transistor ( 118 ) is connected to the gate of the first transistor ( 108 ). The source of the first transistor ( 108 ) is connected to a source of a third transistor ( 120 ). A gate and a drain of the third transistor ( 120 ) are connected together to a gate of the second transistor ( 118 ) and to a fourth port ( 122 ), which is connected to a second current sink ( 124 ). According to the invention the feedthrough error is constant irrespective of the input signal level.
1. An analog memory circuit comprising:
a memory capacitor connected at a first end to a first port, the first port for being connected to a reference potential;
a first transistor, a drain of the first transistor being connected to a second end of the memory capacitor, a source of the first transistor being connected to a second port, the second port for being connected to circuitry for providing an input signal for storage in the memory capacitor, and a gate of the first transistor being connected to a third port, the third port for being connected to a first current sink;
a second transistor, a source of the second transistor being connected to the source of the first transistor and a drain of the second transistor being connected to the gate of the first transistor; and,
a third transistor, a source of the third transistor being connected to the source of the first transistor, a gate and a drain of the third transistor being connected together to a gate of the second transistor and to a fourth port, the fourth port for being connected to a second current sink.
2. An analog memory circuit as in claim 1 comprising:
a fourth transistor, a drain of the fourth transistor being connected to the first end of the memory capacitor, a source of the fourth transistor being connected to a fifth port, the fifth port for being connected to a second reference potential, and a gate of the fourth transistor being connected to a sixth port, the sixth port for being connected to a voltage clock drive.
3. An analog memory circuit as in claim 1 characterized in that the second and the third transistors are designed such that in operation the source and the gate of the first transistor are at substantially equal potential when the first transistor is in an open state for receiving the input signal and providing the same to the memory capacitor for storage therein.
4. An analog memory circuit as in claim 3 characterized in that the second and the third transistors are designed such that in operation a gate potential of the second transistor follows a source potential of the first transistor, the source potential varying in dependence upon the input signal.
5. An analog memory circuit as in claim 4 characterized in that the second and the third transistors are designed such that in operation a drain to source resistance of the second transistor is kept substantially constant.
6. An analog memory circuit as in claim 5 characterized in that the second and the third transistors are designed such that in operation the third transistor provides a gate bias potential such that the drain to source resistance of the second transistor is kept substantially constant.
7. An analog memory circuit as in claim 6 characterized in that the second and the third transistors are substantially equal in size.
8. An analog memory circuit as in claim 1 , further comprising:
a second memory capacitor connected at a first end to the first port;
a fourth transistor, a drain of the fourth transistor being connected to a second end of the second memory capacitor, a source of the fourth transistor being connected to the second port, and a gate of the fourth transistor being connected to a fifth port, the fifth port for being connected to a third current sink; and,
a fifth transistor, a source of the fifth transistor being connected to the source of the fourth transistor, a drain of the fifth transistor being connected to the gate of the fourth transistor, and a gate of the fifth transistor being connected together with the gate of the second transistor and the drain of the third transistor to the fourth port.
9. An analog memory circuit as in claim 8 characterized in that the second and the third transistors are designed such that in operation the source and the gate of the first transistor are at substantially equal potential when the first transistor is in an open state for receiving the input signal and providing the same to the memory capacitor for storage therein, and wherein the fifth and the third transistors are designed such that in operation the source and the gate of the fourth transistor are at substantially equal potential when the fourth transistor is in an open state for receiving the input signal and providing the same to the second memory capacitor for storage therein.
10. An analog memory circuit as in claim 9 characterized in that the second port is connected to a source follower circuitry, and wherein in operation the analog memory circuit performs correlated double sampling.
11. An analog memory circuit as in claim 1 characterized in that the analog memory circuit and the source follower are integrated on a complementary metal-oxide-semiconductor chip.
12. An analog memory circuit as in claim 11 characterized in that the analog memory circuit comprises at least one of NMOS and PMOS components.
13. An analog memory circuit as in claim 11 characterized in that the complementary metal-oxide-semiconductor chip is an imaging pixel detector.
14. A storage medium having stored therein executable commands for execution on a processor, the executable commands for when executed resulting in an integrated circuit design of an analog memory circuit comprising:
a memory capacitor connected at a first end to a first port, the first port for being connected to a reference potential;
a first transistor, a drain of the first transistor being connected to a second end of the memory capacitor, a source of the first transistor being connected to a second port, the second port for being connected to circuitry for providing an input signal for storage in the memory capacitor, and a gate of the first transistor being connected to a third port, the third port for being connected to a first current sink;
a second transistor, a source of the second transistor being connected to the source of the first transistor and a drain of the second transistor being connected to the gate of the first transistor; and,
a third transistor, a source of the third transistor being connected to the source of the first transistor, a gate and a drain of the third transistor being connected together to a gate of the second transistor and to a fourth port, the fourth port for being connected to a second current sink.
15. A storage medium having stored therein executable commands for execution on a processor, the executable commands for when executed resulting in an integrated circuit design of an analog memory circuit as in claim 14 comprising:
a second memory capacitor connected at a first end to the first port;
a fourth transistor, a drain of the fourth transistor being connected to a second end of the second memory capacitor, a source of the fourth transistor being connected to the second port, and a gate of the fourth transistor being connected to a fifth port, the fifth port for being connected to a third current sink; and,
a fifth transistor, a source of the fifth transistor being connected to the source of the fourth transistor, a drain of the fifth transistor being connected to the gate of the fourth transistor, and a gate of the fifth transistor being connected together with the gate of the second transistor and the drain of the third transistor to the fourth port.
16. A storage medium having stored therein executable commands for execution on a processor, the executable commands for when executed resulting in an integrated circuit design of an analog memory circuit as defined in claim 14 comprising:
a fourth transistor, a drain of the fourth transistor being connected to the first end of the memory capacitor, a source of the fourth transistor being connected to a fifth port, the fifth port for being connected to a second reference potential, and a gate of the fourth transistor being connected to a sixth port, the sixth port for being connected to a voltage clock drive.