Transmitter comprising a pulse width pulse position modulator and method thereof
View Patent ↗A baseband signal generator ( 102 a ) provides a polar signal (A, I p) to a processing sub-unit ( 704 p ). The processing sub-unit ( 704 p ) receives furthermore feedback signals from a down converting unit ( 704 c ) which feedback signals are used to determine the magnitude (B) of the amplified output signal and the actual error phase. The magnitude (A) of the polar signal and the determined magnitude (B) are applied to a comparator ( 710 ) having its output connected to the input of a predistortion unit ( 214, 216 ). The output of the predistortion unit ( 214, 216 ) is connected to the input of a pulse width modulating unit ( 210, 212 ) which comprises a mapping unit ( 210 ) outputting two constant magnitude signals. The actual error phase and the phase component of the polar signal are used to generate a corrected phase component which is applied to a further mapping unit ( 202 ) forming part of a phase modulating unit ( 202, 204 ). The output signals of this phase modulating unit ( 202, 204 ) are applied to the pulse width modulating unit ( 210, 212 ) providing finally two pulse width pulse position modulated signals. These signals are applied to the switching amplifier ( 110 ).
1. An apparatus comprising:
a signal generator ( 102 , 102 a ) configured to generate a polar signal,
a pulse width modulating unit ( 108 ) configured to modulate the polar signal,
an amplifier unit ( 110 ) configured to amplify the modulated signal,
a feedback loop path ( 104 a , 504 a , 704 a , 804 a ) configured to correct the modulated signal using an error signal,
wherein the feedback loop path comprises a converting and processing unit ( 104 504 , 704 , 804 ) configured for down converting the amplified signal and correcting the generated signal using the error signal.
2. The apparatus according to claim 1 , wherein the apparatus comprises a predistortion unit ( 106 ) configured to predistort the generated signal.
3. The apparatus according to claim 2 , wherein the predistortion unit ( 106 ) is configured to determine a phase shift function depending on the generated signal.
4. The apparatus according to claim 2 , wherein the predistortion unit ( 106 ) comprises a first determining unit ( 214 ) configured to determine a duty cycle function depending on the generated signal.
5. The apparatus according to claim 4 , wherein the predistortion unit ( 106 ) comprises a second determining unit ( 216 ) configured to determine a phase shift function depending on the determined duty cycle function.
6. The apparatus according to claim 1 , further comprising a pulse position modulating unit ( 208 ) configured to process a phase component of the generated signal.
7. The apparatus according to claim 6 , wherein the pulse position modulating unit ( 208 ) comprises a first mapping unit ( 202 ) configured to map the phase component to at least one suitable function according to a chosen implementation of the pulse position modulating unit ( 208 ).
8. The apparatus according to claim 6 , wherein the pulse position modulating unit ( 208 ) comprises a first up converting unit ( 204 ).
9. The apparatus according to claim 3 , wherein the pulse width modulating unit ( 108 ) comprises a second mapping unit ( 210 ) configured to map the phase shift function to at least one suitable function according to a chosen implementation of the pulse width modulating unit ( 108 ).
10. The apparatus according to claim 1 , wherein the pulse width-modulating unit ( 108 ) comprises a second up converting unit ( 212 ).
11. The apparatus according to claim 6 , wherein the pulse width modulating unit ( 108 ) and the pulse position modulating unit ( 208 ) are arranged as one pulse width pulse position modulating unit ( 608 ).
12. The apparatus according to claim 1 , wherein the converting and processing unit ( 704 , 804 ) comprises a converting subunit ( 704 c ) a processing subunit ( 704 p , 804 p ).
13. The apparatus according to claim 12 , wherein the converting subunit ( 704 c , 804 c ) of the converting and processing unit ( 704 , 804 ) comprises at least one multiplier and/or at least one low pass filter and/or at least one delay element.
14. The apparatus according to claim 12 , wherein the processing subunit ( 704 p , 804 p ) of the converting and processing unit ( 704 , 804 ) comprises at least one of: an envelope detecting unit ( 706 ), (B) a phase detecting unit ( 708 , 808 ).
15. The apparatus according to claim 12 , wherein the processing subunit ( 704 p , 804 p ) of the converting and processing unit ( 704 , 804 ) comprises at least one of:
a first comparing unit ( 710 ) and a first integrator ( 712 ) for correcting an amplitude component,
a second comparing unit ( 816 ) and a second integrator ( 818 ) for correcting a phase component.
16. The apparatus according to claim 12 , wherein the converting subunit ( 704 c , 804 c ) is implemented in the analogue domain ( 712 , 812 ) and the processing subunit ( 704 p , 804 p ) is implemented in the digital domain ( 702 , 802 ).
17. A transmitter comprising an apparatus according to claim 1 .
18. A method comprising:
generating a polar signal,
modulating the polar signal using pulse width modulation,
amplifying the modulated signal,
down converting the amplified signal, and
generating an error signal to correct the generated signal.
19. The method of claim 18 , further comprising processing a phase component of the generated signal, wherein processing the phase component includes mapping the phase component to at least one suitable function according to a chosen implementation of pulse width modulation.