IP Library › Granted Patent US 8,572,342

Granted Patent B2

US 8,572,342 · App. 12/747,086 · Granted Oct 29, 2013

Data transfer device with confirmation of write completion and method of controlling the same

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Quick Facts

Patent No.: US 8,572,342
App. No.: 12/747,086
Granted: Oct 29, 2013
Kind: B2

External Links

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Abstract

A data transfer device that confirms completion of writing into a memory on transferring data to the memory via a bus through which a response indicating completion of data writing in the memory is not sent back includes an inter-memory data transfer control unit performing data transfer between the memories. When the inter-memory data transfer control unit detects switching of a write destination memory from a first memory to a second memory, in order to confirm that writing into the first memory is completed, the inter-memory data transfer control unit performs confirmation of write completion as to the first memory by a procedure different from writing into the memory. When a data transfer with a designated transfer length is completed, in order to confirm that writing is completed as to the write destination memory at the end of the data transfer, the inter-memory data transfer control unit performs confirmation of write completion as to the write destination memory at the end of the transfer by the procedure different from writing into the memory. The inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of write completion.

Claims (81)

1. A data transfer device that transfers data to a memory according to an instruction from a processor via a bus through which a response indicating completion of data writing in the memory is not sent back, comprising:

an inter-memory data transfer control unit performing data transfer between the memories, the inter-memory data transfer control unit including

an operation start trigger receiving unit for receiving an operation start trigger from the processor,

a parameter acquiring unit for acquiring a transfer instruction parameter including information on a data transfer instruction created by the processor,

a read unit for reading data from the memory designated by the transfer instruction parameter,

a write unit for writing the data read by the read unit into the memory designated by the transfer instruction parameter, wherein

when the write unit detects switching of a write destination memory from a first memory to a second memory, in order to confirm that writing into the first memory is completed, the write unit performs confirmation of write completion as to the first memory by a procedure different from writing into the memory,

the inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of the write completion.

2. The data transfer device according to claim 1 , wherein

in order to confirm that writing into the memory is completed, the write unit of the inter-memory data transfer control unit performs reading from the memory through the same bus as used in writing into the memory as the procedure different from writing into the memory.

3. The data transfer device according to claim 1 , wherein

in order to confirm that writing into the memory is completed, the write unit of the inter-memory data transfer control unit performs access to a register in a memory controller through the same bus as used in writing into the memory as the procedure different from writing into the memory.

4. The data transfer device according to claim 3 , wherein

the memory controller is enabled to refer to at least one register provided in the memory controller for at least a number of times of writing by the memory controller.

5. The data transfer device according to claim 4 , wherein

in order to confirm that writing into the memory is completed, the inter-memory data transfer control unit performs reading from the register enabled to referring for the number of times of writing by the memory controller through the same bus as used in writing into the memory as the procedure different from writing into the memory, and

the inter-memory data transfer control unit compares a value read from the register with the number of times of writing by the inter-memory data transfer control unit and confirms whether the data transfer is normally performed.

6. The data transfer device according to claim 1 , wherein

in order to confirm that writing into the memory is completed, the inter-memory data transfer control unit includes a write completion confirmation request/response processing unit for processing a write completion confirmation request dedicated to requesting for securing writing and a write completion confirmation response for response to the write completion confirmation request as the procedure different from writing into the memory,

the inter-memory data transfer control unit confirms completion of the writing by sending the write completion confirmation request and receiving the write completion confirmation response.

7. The data transfer device according to claim 1 , wherein

the data transfer device includes a signal line between the inter-memory data transfer control unit and a memory controller for confirmation of securing writing and for response to the confirmation request,

in order to confirm that writing into the memory is completed, as the procedure different from writing into the memory, the inter-memory data transfer control unit sends a signal for requesting confirmation of securing writing to the memory controller,

the inter-memory data transfer control unit receives a signal of completion of securing writing that the memory controller having received the signal for requesting confirmation of securing writing sends to a request source as a response to the request for confirmation of securing writing when the memory controller detects completion of a requested writing, and

the inter-memory data transfer control unit confirms completion of writing by receiving the signal of completion of securing writing.

8. The data transfer device according to claim 1 , wherein

the inter-memory data transfer control unit detects a timing of switching of the write destination memory from the first memory to the second memory by switching of an access destination memory controller.

9. The data transfer device according to claim 1 , wherein

the inter-memory data transfer control unit determines a timing of switching of the write destination memory from the first memory to the second memory with reference to an access destination address of the memory.

10. The data transfer device according to claim 9 , wherein

the inter-memory data transfer control unit determines a timing of switching of the write destination memory from the first memory to the second memory by the memory controller.

11. The data transfer device according to claim 9 , wherein

the inter-memory data transfer control unit determines a timing of switching of the write destination memory from the first memory to the second memory by the DIMM of the memory.

12. The data transfer device according to claim 9 , wherein

the inter-memory data transfer control unit determines a timing of switching of the write destination memory from the first memory to the second memory by the bank of the memory.

13. The data transfer device according to claim 1 , wherein

the transfer instruction parameter includes at least, as the information on a data transfer instruction, a start address of a transfer source memory, at least one start address of a transfer destination memory, necessity information on whether or not check of completion of writing to each transfer destination memory, and a transfer data length,

when the write unit detects switching of the write destination memory from the first memory to the second memory, in order to confirm that writing into the first memory is completed, the write unit determines whether or not performing confirmation of write completion as to the first memory based on the necessity information in the transfer instruction parameter,

when the write unit determines that the confirmation of write completion is required, the write unit performs confirmation of write completion as to the first memory by the procedure different from writing into the memory,

when the write unit determines that the confirmation of write completion is required, the write unit performs confirmation of write completion as to the write destination memory at the end of the data transfer by the procedure different from writing into the memory.

14. The data transfer device according to claim 1 , wherein

the inter-memory data transfer control unit includes two different-operation start trigger receiving units,

if the inter-memory data transfer control unit is started by receiving the operation start trigger from one of the operation start trigger receiving units, when the inter-memory data transfer control unit detects switching of a write destination memory from the first memory to the second memory, in order to confirm that writing into the first memory is completed, the inter-memory data transfer control unit performs confirmation of write completion as to the first memory by the procedure different from writing into the memory,

when a data transfer instructed by the processor is completed, in order to confirm that writing into the memory is completed as to the write destination memory at the end of the data transfer, the inter-memory data transfer control unit performs confirmation of write completion as to the write destination memory at the end of the data transfer by the procedure different from writing into the memory, and

the inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of write completion;

if the inter-memory data transfer control unit is started by receiving the operation start trigger from the other one of the operation start trigger receiving units, the inter-memory data transfer control unit omits performing confirmation of write completion as to the write destination memory, and

the inter-memory data transfer control unit notifies the processor of completion of the inter-memory data transfer.

15. A data transfer method for transferring data to a memory via a bus through which a response indicating completion of data writing in the memory is not sent back, using an inter-memory data transfer control unit performing data transfer between the memories according to an instruction from a processor, comprising:

when the inter-memory data transfer control unit receives an operation start trigger from the processor,

acquiring by the inter-memory data transfer control unit a transfer instruction parameter including information on a data transfer instruction created by the processor,

reading by the inter-memory data transfer control unit repetitively data from the memory designated by the transfer instruction parameter until a data length of the read data amounts to a transfer length designated by the transfer instruction parameter,

writing by the inter-memory data transfer control unit repetitively the read data to the memory designated by the transfer instruction parameter until a data length of the written data amounts to a transfer length designated by the transfer instruction parameter on data writing by the inter-memory data transfer control unit,

when the inter-memory data transfer control unit detects switching of a write destination memory from a first memory to a second memory, in order to confirm that writing into the first memory is completed, performing by the inter-memory data transfer control unit confirmation of write completion as to the first memory by a procedure different from writing into the memory,

when a data transfer instructed by the processor is completed, in order to confirm that writing into the memory is completed as to the write destination memory at the end of the data transfer, performing by the inter-memory data transfer control unit confirmation of write completion as to the write destination memory at the end of the data transfer by the procedure different from writing into the memory, and notifying the processor of completion of an inter-memory data transfer based on the confirmation of write completion by the inter-memory data transfer control unit.

16. The data transfer method according to claim 15 , wherein

in order to confirm that writing into the memory is completed, the inter-memory data transfer control unit performs reading from the memory through the same bus as used in writing into the memory as the procedure different from writing into the memory.

17. The data transfer method according to claim 15 , wherein

in order to confirm that writing into the memory is completed, the inter-memory data transfer control unit performs reading from a register in a memory controller through the same bus as used in writing into the memory as the procedure different from writing into the memory.

18. The data transfer method according to claim 17 , wherein

19. The data transfer method according to claim 15 , wherein

in order to confirm that writing into the memory is completed, the inter-memory data transfer control unit confirms completion of the writing by sending a write completion confirmation request dedicated to requesting for securing writing and normally receiving a write completion confirmation response for responding to the write completion confirmation request, as the procedure different from writing into the memory.

20. The data transfer method according to claim 15 , wherein

21. The data transfer method according to claim 15 , wherein

22. The data transfer method according to claim 21 , wherein

the inter-memory data transfer control unit manages a timing of switching of the write destination memory from the first memory to the second memory by the memory controller.

23. The data transfer method according to claim 21 , wherein

the inter-memory data transfer control unit manages a timing of switching of the write destination memory from the first memory to the second memory by the DIMM of the memory.

24. The data transfer method according to claim 21 , wherein

the inter-memory data transfer control unit manages a timing of switching of the write destination memory from the first memory to the second memory by the bank of the memory.

25. The data transfer method according to claim 15 , wherein

on data writing by the inter-memory data transfer control unit,

when the inter-memory data transfer control unit detects switching of the write destination memory from the first memory to the second memory, the inter-memory data transfer control unit determines whether or not performing confirmation of write completion as to the first memory based on necessity information on whether or not confirmation of completion of writing to each transfer destination memory in the transfer instruction parameter,

when the inter-memory data transfer control unit determines that the confirmation of write completion is required, the inter-memory data transfer control unit performs confirmation of write completion as to the first memory by the procedure different from writing into the memory,

when a data transfer instructed by the processor is completed, the inter-memory data transfer control unit determines whether or not performing confirmation of write completion as to the write destination memory at the end of the data transfer based on the necessity information in the transfer instruction parameter, and

when the inter-memory data transfer control unit determines that the confirmation of write completion is required, the inter-memory data transfer control unit performs confirmation of write completion as to the write destination memory at the end of the data transfer by the procedure different from writing into the memory.

Assignments (2)

COMPANY SPLIT Recorded Aug 20, 2024

From: HITACHI, LTD.

To: HITACHI VANTARA, LTD.

Reel/Frame 069518/0761 →

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2010

From: ARAI, MASAHIRO; HIRAYAMA, HIROSHI; TAKADA, MASANORI; KANAYAMA, HIROSHI; FUKUDA, HIDEAKI

To: HITACHI, LTD.

Reel/Frame 024510/0978 →