Asynchronously scheduling memory access requests
A data processing system employs a scheduler to schedule pending memory access requests and a memory controller to service scheduled pending memory access requests. The memory access requests are asynchronously scheduled with respect to the clocking of the memory. The scheduler is operated using a clock signal with a frequency different from the frequency of the clock signal used to operate the memory controller. The clock signal used to clock the scheduler can have a lower frequency than the clock used by a memory controller. As a result, the scheduler is able to consider a greater number of pending memory access requests when selecting the next pending memory access request to be submitted to the memory for servicing and thus the resulting sequence of selected memory access requests is more likely to be optimized for memory access throughput.
1. In a data processing system comprising a scheduler and one or more processor cores coupled to a memory by a memory access controller, a method comprising:
scheduling by the scheduler pending memory access requests for servicing by the memory using a first clock signal having a first frequency, the scheduling comprising determining an order in which to service the pending memory access requests; and
servicing the scheduled pending memory access requests by the memory access controller using a second clock signal having a second frequency different than the first frequency, wherein:
the memory access controller maintains memory timing and state information for administering the servicing of the scheduled pending memory access requests;
the determining comprises determining the order based upon predictions by the scheduler of the memory timing and state information maintained by the memory access controller for administering the servicing of the scheduled pending memory access requests; and
the scheduling includes removing the pending access requests from a queue of pending memory access requests and sending them to the memory access controller for servicing.
2. The method of claim 1 , wherein the first frequency is lower than the second frequency.
3. The method of claim 1 , wherein scheduling pending memory access requests comprises scheduling pending memory access requests using first memory timing and state information for memory access requests previously selected for servicing and using second memory timing and state information for the pending memory access requests.
4. The method of claim 3 , wherein the first memory timing and state information comprises information predicting, for each bank of the memory, an open row of the bank and information predicting at least one of: a time remaining before an activate operation can be initiated for the bank; a memory write-to-precharge delay, a memory read-to-precharge delay, and a time remaining before a precharge operation can be initiated for the bank.
5. The method of claim 4 , further comprising:
determining a relationship between the first frequency and the second frequency; and
determining, based on the relationship, at least one of: a first minimum delay between initiation of a precharge operation to close a row of a bank of the memory and initiation of an activation operation to open a different row of the bank; and a second minimum delay between initiation of an activate operation for a bank of the memory and subsequent initiation of a precharge operation for the bank, wherein the first memory timing information for the rows of the banks of the memory is stated in terms of the second frequency, and the determining the at least one comprises converting, based on the relationship, the first memory timing information to memory timing information stated in terms of the first frequency; wherein the time remaining before an activate operation can be initiated for the bank is initially set based on the first minimum delay; and
wherein the time remaining before a precharge operation can be initiated for the bank is initially set based on the second minimum delay.
6. The method of claim 4 , wherein the second memory timing and state information comprises information identifying which pending memory access requests are addressed to a common page of the memory.
7. The method of claim 1 , wherein the scheduling further comprises:
maintaining by the scheduler the predictions of the memory timing and state information;
scheduling by the scheduler one of the pending memory access requests for servicing, the pending memory access request a request for access to a row of a bank of the memory;
setting a row active time parameter of the predictions of the memory timing and state information for the row to a first fixed value based upon the scheduling;
setting a row precharge time parameter of the predictions of the memory timing and state information for the row to a second fixed value based upon the scheduling; and
decrementing both the row active time parameter and the row precharge time parameter per each clock cycle of the first clock signal.
8. The method of claim 7 , wherein:
the setting the row active time parameter and the setting the row precharge time parameter comprise maintaining a table, the table containing entries for a row active time parameter and a row precharge time parameter for a row of each bank of the banks of memory; and
the setting the row active time parameter comprises resetting the value of the row active time parameter based upon sending another of the pending memory access requests to the memory controller for servicing.
9. A method performed in a data processing system comprising one or more processor cores, a memory, a memory controller to conduct memory access operations with the memory, and a scheduler to schedule pending memory access requests for servicing by the memory, the method comprising:
operating the scheduler in a first clock domain associated with a first clock signal having a first frequency, wherein the operating comprises determining an order in which the pending memory access requests are serviced by the memory; and
operating the memory controller in a second clock domain associated with a second clock signal having a second frequency different than the first frequency, wherein:
memory controller maintains memory timing and state information for administering the servicing of the scheduled pending memory access requests;
the scheduler maintains predictions of the memory timing and state information maintained by the memory controller for administering the servicing of the pending memory access requests;
the determining comprises determining the order based upon the predictions maintained by the scheduler of the memory timing and state information maintained by the memory controller for administering the servicing of the pending memory access requests; and
the scheduling comprises removing the pending access requests from a queue of pending memory access requests and sending them to the memory controller for servicing.
10. The method of claim 9 , wherein the first frequency is lower than the second frequency.
11. The method of claim 9 , further comprising operating the memory in the second clock domain.
12. The method of claim 9 , wherein the scheduler is to schedule pending memory access requests using first memory timing and state information for memory access requests previously selected for servicing and using second memory timing and state information for the pending memory access requests.
13. The method of claim 12 , wherein:
the first memory timing and state information comprises information predicting, for each bank of the memory, an open row of the bank and information predicting at least one of: a time remaining before an activate operation can be initiated for the bank; and a time remaining before a precharge operation can be initiated for the bank; and
the predictions of the memory timing and state information maintained by the scheduler comprise the first memory timing and state information; and
the second memory timing and state information comprises information identifying which pending memory access requests are addressed to a common page of the memory.
14. The method of claim 13 , further comprising:
determining a relationship between the first frequency and the second frequency; and
determining, based on the relationship, at least one of: a first minimum delay between initiation of a precharge operation to close a row of a bank of the memory and initiation of an activation operation to open a different row of the bank; and a second minimum delay between initiation of an activate operation for a bank of the memory and subsequent initiation of a precharge operation for the bank;
wherein the time remaining before an activate operation can be initiated for the bank is initially set based on the first minimum delay; and
wherein the time remaining before a precharge operation can be initiated for the bank is initially set based on the second minimum delay.
15. A data processing system comprising:
at least one processor;
a memory controller to:
service, using a first clock signal, scheduled memory access requests for a memory, the first clock signal having a first frequency; and
maintain memory timing and state information for administering the servicing of the scheduled memory access requests; and
a scheduler to schedule, using a second clock signal, memory access requests of the data processing system for servicing by the memory controller, the second clock signal having a second frequency different than the first frequency, wherein:
the scheduling comprising determining an order in which to service the pending memory access requests;
the scheduling includes removing pending access requests from a queue of pending memory access requests and sending them to the memory controller for servicing; and
the determining comprises determining the order based upon predictions of the memory timing and state information maintained by the memory access controller for administering the servicing of the scheduled pending memory access requests.
16. The data processing system of claim 15 , wherein the second frequency is lower than the first frequency.
17. The data processing system of claim 15 , wherein the scheduler is to schedule pending memory access requests using first memory timing and state information for memory access requests previously selected for servicing and using second memory timing and state information for the pending memory access requests.
18. The data processing system of claim 17 , wherein:
the first memory timing and state information comprises information predicting, for each bank of the memory, an open row of the bank and information predicting at least one of: a time remaining before an activate operation can be initiated for the bank; and a time remaining before a precharge operation can be initiated for the bank; and
the predictions of the memory timing and state information comprise the first memory tuning and state information.
19. The data processing system of claim 18 , further comprising:
a frequency translation module comprising an input to receive the first clock signal, an input to receive the second clock signal, and an output to provide an indicator of a relationship between the first frequency and the second frequency; and
wherein the scheduler is to determine, based on the relationship, at least one of: a first minimum delay between initiation of a precharge operation to close a row of a bank of the memory and initiation of an activation operation to open a different row of the bank; and a second minimum delay between initiation of an activate operation for a bank of the memory and subsequent initiation of a precharge operation for the bank;
wherein the time remaining before an activate operation can be initiated for the bank is initially set based on the first minimum delay; and
wherein the time remaining before a precharge operation can be initiated for the bank is initially set based on the second minimum delay.
20. The data processing system of claim 18 , wherein the second memory timing and state information comprises information identifying which pending memory access requests are addressed to a common page of the memory.