IP Library Granted Patent US 8,253,254
Granted Patent B2
US 8,253,254 · App. 12/748,737 · Granted Aug 28, 2012

Semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 8,253,254
App. No.
12/748,737
Granted
Aug 28, 2012
Kind
B2
Abstract

A semiconductor device has a first insulation film defining a plurality of contact holes arranged along a predetermined direction. A plurality of first contact plugs is respectively formed in the contact holes. A second insulation film is formed on the first insulation film and defining an opening to expose a predetermined region of the first insulation film including a region where the first contact plugs are formed. A plurality of interconnections are formed to extend across the opening and to be in contact with top surfaces of the first contact plugs, respectively.

Claims (36)

1. A semiconductor device comprising:

a first interlayer film defining a plurality of contact holes arranged along a first direction;

a plurality of contact plugs filled in the contact holes, respectively;

a second interlayer film formed on the first interlayer film and having an opening to expose a predetermined region of the first interlayer film including a region where the contact plugs are disposed; and

a plurality of interconnections formed to extend across the opening and to be in contact with top surfaces of the contact plugs, respectively, wherein each interconnection extends in a second direction being crossed to the first direction,

wherein the top surfaces of the contact plugs are lower in level than an interface between the first interlayer film and the second interlayer film.

2. The semiconductor device as claimed in claim 1 , wherein the first interlayer film includes a portion which is recessed from a surface of the first interlayer film within the opening.

3. The semiconductor device as claimed in claim 1 , wherein the first interlayer film is disposed on a semiconductor substrate; and

the semiconductor device further comprises:

a recessed portion formed in the region of the first insulation film exposed by the opening, the recessed portion including a top surface which is lower than a level of a top surface of a region of the first insulation film where the opening is not formed.

4. The semiconductor device as claimed in claim 3 , wherein the top surface of the recessed portion in the first insulation film includes a part which is higher in level than the top surfaces of the contact plugs.

5. The semiconductor device as claimed in claim 3 , wherein the interconnections are formed to extend from the recessed portion in the first insulation film via the opening in the second insulation film up to a top surface of the second insulation film such that the interconnections pass across the opening and are connected to the top surfaces of the respective contact plugs.

6. The semiconductor device as claimed in claim 3 , comprising a plurality of sets of the contact plugs, the opening being formed in correspondence with each set thereof.

7. The semiconductor device as claimed in claim 6 , wherein each of the interconnections is connected to the top surfaces of the contact plugs belonging to different sets.

8. The semiconductor device as claimed in claim 3 , further comprising a wiring line disposed on the semiconductor substrate, wherein the top surfaces of the contact plugs are lower in level than a top surface of the wiring line.

9. A semiconductor device comprising;

a first interlayer film having a plurality contact holes arranged in line in a first direction;

a plurality of first contact plugs filling the contact holes, respectively;

a second interlayer film formed over the first interlayer film and the contact plugs, the second interlayer film having an opening which continuously exposes the first contact plugs and respective parts of the first interlayer film around the first contact plugs;

a plurality of interconnections each extending in a second direction, which crosses the first direction, to intersect the opening of the second interlayer film with overlapping an associated one of the first contact plugs; and

a plurality of second contact plugs each intervening between an associated one of the first contact plug and a portion of an associated one of the interconnections,

wherein the top surface of the first contact plugs are lower in level than a top surface of the first interlayer film of a region without the opening of the second interlayer.

10. The semiconductor device as claimed in claim 9 , wherein the first interlayer film is disposed over a semiconductor substrate; and

the semiconductor device further comprises;

a recessed portion in the first interlayer film having a region same as the opening of the second interlayer.

11. The semiconductor device as claimed in claim 10 , wherein the second contact plugs cover a part of the recessed portion in the first interlayer film and a part of the top surface of the second contact plugs and a part of a side face of the second interlayer at a pattern edge of the opening.

12. The semiconductor device as claimed in claim 10 , comprising a plurality of a set of the first contact plugs each including an associated one of the opening of the second interlayer.

13. The semiconductor device as claimed in claim 12 , comprising a plurality of a set of the second contact plugs each connecting an associated one of set of the first contact plugs within the opening of the second interlayer.

14. The semiconductor device as claimed in claim 13 , wherein a plurality of interconnections each connects an associated one of the second contact plugs belonging to different sets.

15. The semiconductor device as claimed in claim 10 , further comprising a wiring line disposed over the semiconductor substrate, wherein the top surface of the contact plugs are lower in level than a top surface of the wiring line.

16. The semiconductor device as claimed in claim 9 , wherein the recessed portion has a stepped bottom surface in the first interlayer film, a part of the bottom surface is higher in level than the top surface of the first contact plugs.

17. A semiconductor device comprising:

a plurality of conductive regions formed apart from each other and disposed in line in a first direction;

an interlayer insulating layer covering the conductive regions and including an opening that exposes at least a part of each of the conductive regions; and

a plurality of interconnections each extending in a second direction, that is substantially perpendicular to the first direction, to cross an associated one of the conductive regions, each of the interconnections including a projection that is in contact with the associated one of the conductive regions, the projection of each of the interconnections being defined in the first direction by a width of an associated one of the interconnections and in the second direction by a width of the opening.

18. The device as claimed in claim 17 , wherein the projection of each of the interconnection comprises a conductive plug formed in the opening of the interlayer insulating layer.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: LONGITUDE SEMICONDUCTOR S.A.R.L.
To: LONGITUDE LICENSING LIMITED
Reel/Frame 046865/0667 →
CHANGE OF NAME Recorded Aug 24, 2016
From: PS5 LUXCO S.A.R.L.
To: LONGITUDE SEMICONDUCTOR S.A.R.L.
Reel/Frame 039793/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2016
From: PS4 LUXCO S.A.R.L.
To: PS5 LUXCO S.A.R.L.
Reel/Frame 039818/0506 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2014
From: ELPIDA MEMORY, INC.
To: PS4 LUXCO S.A.R.L.
Reel/Frame 032884/0589 →
SECURITY AGREEMENT Recorded Jul 29, 2013
From: PS4 LUXCO S.A.R.L.
To: ELPIDA MEMORY INC.
Reel/Frame 032414/0261 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2010
From: UJIHARA, SHINGO
To: ELPIDA MEMORY, INC.
Reel/Frame 024153/0113 →