Apparatus and method to compensate for injection locking
View Patent ↗A circuit and method has a processing unit, a master clock generator for providing a master clock and a plurality of phase-locked loops, each providing a respective clock signal. A plurality of dynamically variable delay circuits each has a plurality of predetermined delay amounts. Clocked circuits are coupled to respective clock signals provided by respective phase-locked loops. A performance detector is coupled to receive the clock signals for determining a center of a quiet zone for at least one of the plurality of phase-locked loops. The phase-locked loops are turned off and on and a respective one of the plurality of dynamically variable delay circuits is set to have a new predetermined value of delay which adjusts an edge of the master clock to a location that permits the data processing system to operate near substantially the center of the quiet zone.
1. In a data processing system having a plurality of phase-locked loops coupled to a master clock, each of the plurality of phase-locked loops providing a respective clock signal to respective clocked circuitry, a method to compensate for injection locking comprising:
(a) turning on at least two of the plurality of phase-locked loops;
(b) setting a dynamically variable delay circuit that is between the master clock and one of the at least two of the plurality of phase-locked loops to have a predetermined value of delay, the dynamically variable delay circuit having a plurality of delay values;
(c) measuring performance of at least one of the plurality of phase-locked loops by using the plurality of delay values to provide a plurality of performance values;
(e) determining a center of a quiet zone of phase difference between clocks of the at least two of the plurality of phase-locked loops;
(f) adjusting, if necessary, a currently selected temporary delay value for the one of the at least two of the plurality of phase-locked loops to an adjusted new temporary delay value that corresponds to substantially the center of the quiet zone; and
(g) during operation of the data processing system, turning off the at least two of the plurality of phase-locked loops and repeating (a) through (f).
2. The method of claim 1 further comprising:
after turning on the at least two of the plurality of phase-locked loops for a first time, setting the dynamically variable delay circuit to have a minimum value of delay as the predetermined value of delay; and
incrementing delay values in a sequentially increasing order to measure performance for a remainder of the plurality of delay values.
3. The method of claim 1 further comprising:
after turning on the at least two of the plurality of phase-locked loops for a first time, setting the dynamically variable delay circuit to have a maximum value of delay as the predetermined value of delay; and
decrementing delay values in a sequentially decreasing order to measure performance for a remainder of the plurality of delay values.
4. The method of claim 1 further comprising:
measuring performance of the at least one of the plurality of phase-locked loops by measuring a bit error rate (BER) of data communicated by first clocked circuitry clocked by a first of the at least two of the plurality of phase-locked loops and second clocked circuitry clocked by a second of the at least two of the plurality of phase-locked loops;
determining lower and upper limits of delay values to define the quiet zone of phase difference where clock jitter amplitude is lower than outside of the quiet zone of phase difference; and
calculating the center of the quiet zone as an average of the lower and upper limits of delay values.
5. The method of claim 1 further comprising:
measuring performance of the at least one of the plurality of phase-locked loops by measuring clock jitter at an output of each of the at least two of the plurality of phase-locked loops for each of the plurality of delay values;
determining lower and upper limits of delay values to define the quiet zone of phase difference where clock jitter amplitude is lower than outside of the quiet zone of phase difference; and
calculating the center of the quiet zone as an average of the lower and upper limits of delay values.
6. The method of claim 1 further comprising:
measuring performance of the at least one of the plurality of phase-locked loops by determining a position of each transition between high and low amplitudes for a series of data communicated by first clocked circuitry to define clock jitter for the at least two of the plurality of phase-locked loops;
determining lower and upper limits of delay values to define the quiet zone of phase difference where clock jitter amplitude is lower than outside of the quiet zone of phase difference; and
calculating the center of the quiet zone as an average of the lower and upper limits of delay values.
7. A data processing system comprising:
a master clock generator for providing a master clock;
a plurality of phase-locked loops coupled to the master clock generator, each of the plurality of phase-locked loops providing a respective clock signal;
a plurality of dynamically variable delay circuits, each coupled between the master clock generator and a respective one of the plurality of phase-locked loops and having a plurality of predetermined delay amounts;
a plurality of clocked circuitry portions comprising respective clocked circuits coupled to the respective clock signal of a predetermined one of the plurality of phase-locked loops;
a performance detector coupled to the plurality of clocked circuitry portions for determining a center of a quiet zone of phase difference between clocks of at least two of the plurality of phase-locked loops; and
a processing unit coupled to the performance detector and the plurality of dynamically variable delay circuits, the processing unit selectively turning off the at least two of the plurality of phase-locked loops, turning on the at least two of the plurality of phase-locked loops and setting a respective one of the plurality of dynamically variable delay circuits to have a new predetermined value of delay which readjusts delay to a value that adjusts an edge of the master clock to a location that permits the data processing system to operate near substantially the center of the quiet zone.
8. The data processing system of claim 7 wherein after turning on the at least two of the plurality of phase-locked loops for a first time, the processing unit sets the respective one of the dynamically variable delay circuits to have a minimum value of delay as a predetermined value of delay and incrementing delay values in a sequentially increasing order to measure performance for a remainder of the plurality of delay values.
9. The data processing system of claim 7 wherein after turning on the at least two of the plurality of phase-locked loops for a first time, the processing unit sets the dynamically variable delay circuit to have a maximum value of delay as a predetermined value of delay and decrements delay values in a sequentially decreasing order to measure performance for a remainder of the plurality of delay values.
10. The data processing system of claim 7 wherein the performance detector measures performance of the at least one of the plurality of phase-locked loops by measuring a bit error rate (BER) of data communicated by first clocked circuitry clocked by a first of the at least two of the plurality of phase-locked loops and second clocked circuitry clocked by a second of the at least two of the plurality of phase-locked loops, the performance detector determining lower and upper limits of delay values to define the quiet zone of phase difference where clock jitter amplitude is lower than outside of the quiet zone of phase difference and calculates the center of the quiet zone as an average of the lower and upper limits of delay values.
11. The data processing system of claim 7 wherein the performance detector measures performance of the at least two of the plurality of phase-locked loops by measuring clock jitter at an output of at least one of the plurality of phase-locked loops for each of the plurality of delay values and determines lower and upper limits of delay values to define the quiet zone of phase difference where clock jitter amplitude is lower than outside of the quiet zone of phase difference, the performance detector calculating the center of the quiet zone as an average of the lower and upper limits of delay values.
12. The data processing system of claim 7 wherein the performance detector measures performance of at least one of the plurality of phase-locked loops by determining a position of each transition between high and low amplitudes for a series of data communicated by first clocked circuitry to define clock jitter for the at least one of the plurality of phase-locked loops and determines lower and upper limits of delay values to define the quiet zone of phase difference where clock jitter amplitude is lower than outside of the quiet zone of phase difference, the performance detector calculating the center of the quiet zone as an average of the lower and upper limits of delay values.
13. A method comprising:
providing a master clock signal to at least a first phase-locked loop and a second phase-locked loop;
injecting a predetermined variable delay to the master clock signal prior to said providing the master clock signal to the second phase-locked loop;
providing first and second clock signals respectively to first and second clocked circuits respectively from the first phase-locked loop and the second phase-locked loop;
measuring performance of the first and second clock signals in response to delaying the master clock signal to the second phase-locked loop using a plurality of differing delay values resulting in a plurality of performance values;
determining a center of a quiet zone of phase difference between the first and second clock signals;
adjusting, if necessary, a currently selected temporary delay value for the master clock signal coupled to the second phase-locked loop to an adjusted new temporary delay value that corresponds to substantially the center of the quiet zone; and
selectively repeating said measuring, determining and adjusting during functional operation of the first and second clocked circuits.
14. The method of claim 13 further comprising:
after turning on the first and second phase-locked loops for a first time, setting the dynamically variable delay to have a minimum value of delay as the predetermined variable delay; and
incrementing delay values in a sequentially increasing order to measure performance for a remainder of the plurality of delay values.
15. The method of claim 13 further comprising:
after turning on the first and second phase-locked loops for a first time, setting the dynamically variable delay circuit to have a maximum value of delay as the predetermined variable delay; and
decrementing delay values in a sequentially decreasing order to measure performance for a remainder of the plurality of delay values.
16. The method of claim 13 further comprising:
measuring performance of the first and second phase-locked loops by measuring a bit error rate (BER) of data communicated by the first clocked circuit clocked by the first phase-locked loop and second clocked circuit clocked by the second phase-locked loops;
determining lower and upper limits of delay values to define the quiet zone of phase difference where clock jitter amplitude is lower within the quiet zone of phase difference than outside the quiet zone of phase difference; and
calculating the center of the quiet zone as an average of the lower and upper limits of delay values.
17. The method of claim 13 further comprising:
measuring performance of the first and second phase-locked loops by measuring clock jitter at an output of each of the first and second phase-locked loops for each of the plurality of delay values;
determining lower and upper limits of delay values to define the quiet zone of phase difference where clock jitter amplitude is lower than outside of the quiet zone of phase difference; and
calculating the center of the quiet zone as an average of the lower and upper limits of delay values.
18. The method of claim 13 further comprising:
measuring performance of the at least two of the plurality of phase-locked loops by determining a position of each transition between high and low amplitudes for a series of data communicated by first clocked circuitry to define clock jitter for the at least two of the plurality of phase-locked loops;
determining lower and upper limits of delay values to define the quiet zone of phase difference where clock jitter amplitude is lower than outside of the quiet zone of phase difference; and
calculating the center of the quiet zone as an average of the lower and upper limits of delay values.
19. The method of claim 13 further comprising:
coupling additional pairs of phase-locked loops to the same master clock for clocking additional clocked circuits;
measuring performance of clock signals provided by said additional pairs of phase-locked loops in response to delaying the master clock signal using a plurality of differing delay values to provide a plurality of performance values;
determining a center of a quiet zone of phase difference between the clock signals provided by said additional pairs of phase-locked loops;
adjusting, if necessary, a currently selected temporary delay value for the master clock signal coupled to predetermined ones of the additional pairs of phase-locked loops to adjusted new temporary delay values that correspond to the center of the quiet zone; and
selectively repeating said measuring, determining and adjusting during functional operation of the additional clocked circuits.
20. The method of claim 13 further comprising:
selectively repeating said measuring, determining and adjusting during functional operation of the first and second clocked circuits in response to detecting any one of a change in temperature, voltage, master clock frequency, phase-locked loop frequency or a change in power management configuration.