Liquid crystal display and panel therefor
View Patent ↗A flat panel display having an improved picture quality is disclosed. In one embodiment, a first pixel electrode and a second pixel electrode are formed in each subpixel area. The electrodes enclose an open space (gap) such that their outer boundary has a substantially rectangular shape. The flat panel display may also include a capacitance electrode coupled to the second pixel electrode to form a coupling capacitor. In use, the coupling capacitor operates such that a magnitude of a voltage applied to the first pixel electrode is lower than an applied data voltage, and a magnitude of a voltage applied to the second pixel electrode is higher than an applied voltage. The different voltages operate such that a tilt direction of LC molecules disposed above the first pixel electrode differs from a tilt direction of LC molecules disposed above the second pixel electrode.
1. A flat panel display, comprising:
a substrate;
a gate line disposed on the substrate;
a signal line extended substantially parallel to the gate line;
a data line intersecting the gate line;
a first sub pixel electrode and a second sub pixel electrode disposed on the substrate;
a first thin film transistor comprising a first terminal connected to the gate line, a second terminal connected to the data line, and a third terminal connected to the first sub pixel electrode;
a second thin film transistor comprising a first terminal connected to the gate line, a second terminal connected to the data line, and a third terminal connected to the second sub pixel electrode; and
a third thin film transistor comprising a first terminal connected to the signal line, a second terminal connected to the first sub pixel electrode, and a third terminal connected to a coupling electrode.
2. The flat panel display of claim 1 , further comprising:
a storage electrode pattern disposed on a same layer as the gate line, and
wherein the coupling electrode a portion of the storage electrode pattern.
3. The flat panel display of claim 2 , wherein a capacitance between the coupling electrode and the storage electrode pattern is different from a capacitance between the first pixel electrode and the storage electrode pattern.
4. The flat panel display of claim 3 , wherein the capacitance between the coupling electrode and the storage electrode pattern ranges from about 1/10 to about ⅓ of the capacitance between the first pixel electrode and the storage electrode pattern.
5. The flat panel display of claim 1 , wherein a ratio of the area of the first sub pixel electrode to the area of the second sub pixel electrode is in a range from about 50:50 to about 80:20.
6. The flat panel display of claim 5 , wherein the first sub pixel electrode has a domain divider.
7. The flat panel display of claim 6 , wherein a parasitic capacitance between the first terminal and the third terminal of the third thin film transistor is larger than a parasitic capacitance between the first terminal and the third terminal of the first thin film transistor.
8. The flat panel display of claim 7 , wherein the signal line is another gate line adjacent to the gate line.
9. The flat panel display of claim 1 , wherein the first sub pixel electrode has a domain divider.
10. The flat panel display of claim 9 , wherein a parasitic capacitance between the first terminal and the third terminal of the third thin film transistor is larger than a parasitic capacitance between the first terminal and the third terminal of the first thin film transistor.
11. The flat panel display of claim 10 , wherein the signal line is another gate line adjacent to the gate line.
12. The flat panel display of claim 1 , wherein a parasitic capacitance between the first terminal and the third terminal of the third thin film transistor is larger than a parasitic capacitance between the first terminal and the third terminal of the first thin film transistor.
13. The flat panel display of claim 12 , wherein the signal line is another gate line adjacent to the gate line.
14. The flat panel display of claim 1 , wherein the signal line is another gate line adjacent to the gate line.
15. A flat panel display, comprising:
a substrate;
a first gate line and a second gate line disposed on the substrate;
a storage electrode pattern disposed on a same layer as the first gate line and the second gate line;
a data line intersecting the first gate line and the second gate line;
a first sub pixel electrode and a second sub pixel electrode disposed on the substrate;
a first thin film transistor including a first terminal connected to the first gate line, a second terminal connected to the data line, and a third terminal connected to the first sub pixel electrode;
a second thin film transistor including a first terminal connected to the first gate line, a second terminal connected to the data line, and a third terminal connected to the second sub pixel electrode; and
a third thin film transistor including a first terminal connected to the second gate line, a second terminal connected to the first sub pixel electrode and a third terminal connected to a coupling electrode which overlaps a portion of the storage electrode pattern.