Integrated semiconductor nanowire device
View Patent ↗A method of making a semiconductor nanowire device includes providing a plurality of spaced semiconductor nanowires on a growth substrate; applying a dielectric material so that it is disposed between the semiconductor nanowires producing a layer of embedded semiconductor nanowires having a top surface opposed to a bottom surface, wherein the bottom surface is defined by the interface with the growth substrate; depositing a first electrode over the top surface of the layer of embedded semiconductor nanowires so that it is in electrical contact with the semiconductor nanowires; joining the first electrode to a device substrate; removing the growth substrate and exposing the bottom surface of the layer of embedded semiconductor nanowires; and depositing a second electrode on the bottom surface of the layer of embedded semiconductor nanowires so that it is in electrical contact with the semiconductor nanowires.
1. A method of making a semiconductor nanowire device comprising:
(a) providing a plurality of spaced semiconductor nanowires on a growth substrate;
(b) applying a dielectric material so that it is disposed between the semiconductor nanowires producing a layer of embedded semiconductor nanowires having a top surface opposed to a bottom surface, wherein the bottom surface is defined by the interface with the growth substrate;
(c) depositing a first electrode over the top surface of the layer of embedded semiconductor nanowires so that it is in electrical contact with the semiconductor nanowires;
(d) joining the first electrode to a device substrate;
(e) removing the growth substrate and exposing the bottom surface of the layer of embedded semiconductor nanowires; and
(f) depositing a second electrode on the bottom surface of the layer of embedded semiconductor nanowires so that it is in electrical contact with the semiconductor nanowires.
2. The method of claim 1 wherein the semiconductor nanowires include type II-VI, III-V, IV-VI or IV semiconductor materials.
3. The method of claim 2 wherein the semiconductor nanowires include core/shell nanowires.
4. The method of claim 3 wherein the core/shell nanowires have cores having discrete internal heterostructure units.
5. The method of claim 2 wherein the nanowires have discrete internal heterostructure units.
6. The method of claim 1 wherein the dielectric material is a polymer dielectric.
7. The method of claim 1 wherein step (c) is provided by vacuum depositing or sputtering the first electrode.
8. The method of claim 1 wherein step (d) includes using a conductive connection material to form an electrical connection between the first electrode and the device substrate.
9. The method of claim 8 wherein the conductive connection material is a metal and step (d) is provided by:
(i) depositing the metallic conductive connection material on the device substrate;
(ii) melting the metallic conductive connection material; and
(iii) placing the first electrode in contact with the metallic conductive connection material to join the first electrode to the device substrate.
10. The method of claim 1 wherein the device substrate is flexible.
11. The method of claim 1 wherein the device substrate is conductive.
12. The method of claim 1 wherein the second electrode of step (f) is deposited in a pattern.
13. The method of claim 1 wherein step (e) includes using mechanical force to remove the device substrate.
14. The method of claim 1 wherein step (e) includes providing energy to weaken the bond between the semiconductor nanowires and the growth substrate to facilitate the removal of the semiconductor nanowires.