Synchronous global controller for enhanced pipelining
View Patent ↗The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.
1. A controller adapted to generate different clock pulses for read and write operations, wherein at least one of said different clock pulses is extended wherein said at least one of said different clock pulses is a write clock pulse.
2. The controller of claim 1 , wherein at least one of said different clock pulses is based on a received signal.
3. The controller of claim 1 further adapted to skew at least one pre-charge signal for at least a read operation.
4. A memory device comprising:
at least one local memory block; and
a global controller coupled to at least said local memory block and adapted to manage timing of read and write operations, wherein said global controller is further adapted to extend a portion of a write clock pulse.
5. The memory device of claim 4 , wherein said global controller is synchronously controlled.
6. The memory device of claim 4 , wherein said local memory block comprises at least one memory cell.
7. The memory device of claim 4 , wherein said local memory block comprises at least one local decoder.
8. The memory device of claim 4 , wherein said local memory block comprises at least one local sense amp.
9. The memory device of claim 4 , wherein said local memory block comprises at least one local controller.
10. A method for processing read and write operations in a memory architecture having a synchronous global controller, the method comprising:
generating control signals; and
skewing at least one write clock pulse with the synchronous global controller.
11. The method of claim 10 , wherein the read and write operations are completed in a single cycle.
12. The method of claim 11 , wherein said single cycle is faster than an external clock cycle.
13. The method of claim 10 , wherein said memory architecture comprises at least one memory cell.
14. The method of claim 10 , wherein said memory architecture comprises at least one local decoder.
15. The method of claim 10 , wherein said memory architecture comprises at least one local sense amp.
16. The method of claim 10 , wherein said memory architecture comprises at least one local controller.
17. The method of claim 10 , wherein the local controller is adapted to generate different clock pulses for read and write operations, further adapted to skew at least one pre-charge signal for at least a read operation.
18. A method for processing read and write operations in a memory architecture comprising skewing a clock pulse using a global controller, wherein skewing said clock pulse includes extending a high portion of said clock pulse using at least one word line interfacing with said global controller.
19. A controller adapted to generate different clock pulses for read and write operations, further adapted to skew at least one pre-charge signal for at least a read operation.
20. The controller of claim 19 , wherein at least one of said different clock pulses is based on a received signal.