System having a plurality of memory devices and data transfer method for the same
The control section performs a write operation, in synchronism with a clock signal, for transferring write data to one of the plurality of memory devices, utilizing: (i) an identification information transmission period during which the control section sends the identification information of a single memory device to all of the plurality of memory devices through the data line to select the single memory device; (ii) a write data transmission period during which the control section sends a single set of write data having a prescribed size to the selected single memory device; and (iii) a response period during which the selected single memory device responds to the control section with a response signal indicating presence or absence of communication error in relation to the received set of write data. Communications between the control section and the selected memory device during the write data transmission period and the response period are repeatedly performed for each transmission of one of plural sets of write data having the prescribed size. The control section sets a frequency of the clock signal during the response period to a lower value than that of the clock signal during the write data transmission period.
1. A system comprising:
a control section; and
a plurality of memory devices that are bus connected to the control section with a clock signal line and a data signal line, each of the plurality of memory devices prestoring identification information for distinguishing the memory device from the other memory devices,
wherein the control section performs a write operation, in synchronism with a clock signal, for transferring write data to one of the plurality of memory devices, utilizing:
(i) an identification information transmission period during which the control section sends the identification information of a single memory device to all of the plurality of memory devices through the data line to select the single memory device;
(ii) a write data transmission period during which the control section sends a single set of write data having a prescribed size to the selected single memory device; and
(iii) a response period during which the selected single memory device responds to the control section with a response signal indicating presence or absence of communication error in relation to the received set of write data,
wherein communications between the control section and the selected memory device during the write data transmission period and the response period are repeatedly performed for each transmission of one of plural sets of write data having the prescribed size, and
the control section sets a frequency of the clock signal during the response period to a lower value than that of the clock signal during the write data transmission period.
2. The system in accordance with claim 1 , wherein
the control section includes a clock generator that generates the clock signal, and an input/output section that performs sending of the write data and receiving of the response signal, and
the plurality of memory devices each includes a data receive/send section that performs receiving of the write data and sending of the response signal, and a response signal generator that generates the response signal.
3. The system in accordance with claim 1 , wherein
during the response period, the selected single memory device completes a process of storing in the selected single memory device the single set of write data that is received immediately prior to the response period.
4. A data transfer method between a control section and a plurality of memory devices that are bus connected to the control section with a clock signal line and a data signal line, each of the plurality of memory devices prestoring identification information for distinguishing the memory device from the other memory devices, the method comprises:
a write operation, performed by the control section in synchronism with a clock signal for transferring write data to one of the plurality of memory devices, the write operation including the steps of:
(i) sending, performed by the control section, the identification information of a single memory device to all of the plurality of memory devices through the data line to select the single memory device;
(ii) sending, performed by the control section, a single set of write data having a prescribed size to the selected single memory device; and
(iii) responding, performed by the selected single memory device, to the control section with a response signal indicating presence or absence of communication error in relation to the received set of write data,
wherein the step of sending a single set of write data and the step of responding to the control section are repeatedly performed for each transmission of one of plural sets of write data having the prescribed size, and a frequency of the clock signal during the response period is set by the control section to a lower value than that of the clock signal during the write data transmission period.
5. The data transfer method in accordance with claim 4 , wherein a process of storing in the selected single memory device the single set of write data that is received immediately prior to the step of responding to the control section is completed in parallel with the step of responding to the control section.