Thin film transistor array panel and method of manufacture

1. A method for manufacturing a thin film transistor array panel, comprising:

forming a gate line on a substrate;

forming an interlayer insulating film on the entire surface of the substrate including the gate line;

forming an opening in the interlayer insulating film;

forming a gate insulator in the opening;

sequentially forming a first conductive layer comprising a transparent conductive oxide and a second conductive layer comprising a metal on the interlayer insulating film and the gate insulator;

sequentially photo-etching the second conductive layer and the first conductive layer to form a data line and conductive members separate from the data line;

removing part of the data line and the second conductive layer of the conductive members to form a pixel electrode including a drain electrode and a source electrode; and

forming an organic semiconductor contacting the source electrode and the drain electrode.

2. The method of claim 1 , wherein the forming of an opening comprises exposing the interlayer insulating film by using a mask having a shielding region, a transmissive region, and a semi-transmissive region.

3. The method of claim 1 , wherein the forming of a data line and the conductive members and the forming of a pixel electrode and a source electrode are carried out by using one mask.

4. The method of claim 3 , wherein the mask has a shielding region, a transmissive region, and a semi-transmissive region.

5. The method of claim 4 , wherein the forming of a data line and the conductive members comprises:

forming a photoresist film on the second conductive layer;

forming a first photoresist pattern and a second photoresist pattern thinner than the first photoresist pattern by exposing the photoresist film by using the mask; and

etching the second conductive layer and the first conductive layer by using the first photoresist pattern and the second photoresist pattern as a mask.

6. The method of claim 5 , wherein the forming of a pixel electrode and a source electrode comprises:

removing the second photoresist pattern; and

etching the second conductive layer of the conductive members by using the first photoresist pattern as a mask.

7. The method of claim 1 , wherein at least one of the forming of a gate insulator and the forming of an organic semiconductor is carried out by an inkjet printing method.

8. A method for manufacturing a thin film transistor array panel, comprising:

forming a gate line on a substrate;

forming an interlayer insulating film having an opening on the gate line;

forming a gate insulator in the opening;

forming a data line including a source electrode and a pixel electrode including a drain electrode on the interlayer insulating film; and

forming an organic semiconductor on the source electrode and the drain electrode, the gate line being formed by using a first mask, the interlayer insulating film being formed by using a second mask, and

the data line including the source electrode and the pixel electrode including the drain electrode being formed by using a third mask.

9. The method of claim 8 , wherein at least one of the forming of a gate insulator and the forming of an organic semiconductor is carried out by an inkjet printing method.

10. The method of claim 8 , wherein the forming of a data line including a source electrode and a pixel electrode including a drain electrode comprises:

sequentially forming first and second conductive layers that have different etching selectivity ratios;

sequentially etching the second conductive layer and the first conductive layer to expose part of the gate insulator; and

partially etching the second conductive layer,

wherein in the partial etching of the second conductive layer, a portion where the second conductive layer remains is the data line and a portion where the second conductive layer is removed is the source electrode, the drain electrode, and the pixel electrode.