Semiconductor device with strain
View Patent ↗A semiconductor device includes: a semiconductor substrate having a p-MOS region; an element isolation region formed in a surface portion of the semiconductor substrate and defining p-MOS active regions in the p-MOS region; a p-MOS gate electrode structure formed above the semiconductor substrate, traversing the p-MOS active region and defining a p-MOS channel region under the p-MOS gate electrode structure; a compressive stress film selectively formed above the p-MOS active region and covering the p-MOS gate electrode structure; and a stress released region selectively formed above the element isolation region in the p-MOS region and releasing stress in the compressive stress film, wherein a compressive stress along the gate length direction and a tensile stress along the gate width direction are exerted on the p-MOS channel region. The performance of the semiconductor device can be improved by controlling the stress separately for the active region and element isolation region.
1. A semiconductor device comprising:
a semiconductor substrate having an n-channel type transistor region and a p-channel type transistor region;
an element isolation region formed in a surface portion of said semiconductor substrate, said element isolation region defining an n-MOS active region in said n-channel type transistor region and a p-MOS active region in said p-channel type transistor region;
an n-MOS gate electrode structure formed above said semiconductor substrate, traversing an intermediate portion of said n-MOS active region and defining an n-MOS channel region under said n-MOS gate electrode structure;
a p-MOS gate electrode structure formed above said semiconductor substrate, traversing an intermediate portion of said p-MOS active region and defining an p-MOS channel region under said p-MOS gate electrode structure;
a contact etch stopper film having a compressive stress, formed above said semiconductor substrate and covering said n-MOS gate electrode structure and said p-MOS gate electrode structure; and
a stress released region selectively formed in said contact etch stopper film above a whole portion of said n-MOS active region and above said element isolation region surrounding said p-MOS active region, said stress released region releasing stress in said contact etch stopper film,
wherein said contact etch stopper film maintains compressive stress only above said p-MOS active region, and exerts compressive stress along gate length direction and tensile stress along gate width direction to said p-MOS channel region.
2. The semiconductor device according to claim 1 , wherein said stress released region is made of an ion implanted region.
3. The semiconductor device according to claim 2 , wherein said element isolation region defines another p-MOS active region adjacent to said p-MOS active region in said p-channel type transistor region, and said stress released region is formed above said element isolation region with respect to the gate width direction of said p-MOS active region and said another p-MOS active region.
4. A semiconductor device according to claim 2 , wherein said ion implanted region is a region where electrically inert impurity ions are implanted.
5. The semiconductor device according to claim 1 , wherein said semiconductor substrate is a silicon substrate having a (001) plane and the gate length direction is along <110> direction.