Method, system and computer-readable code to test flash memory
View Patent ↗A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die.
1. A flash memory device comprising:
a flash memory residing on at least one flash memory die; and
a flash controller residing on a flash controller die separate from the at least one flash memory die, wherein:
the flash memory and the flash controller reside within, reside on, or are attached to a common housing; and
the flash controller is configured to execute at least one test program to test the at least one flash memory die.
2. The flash memory device of claim 1 , wherein the at least one test program is executed in response to a signal received from an external testing device.
3. The flash memory device of claim 2 , wherein the signal includes electrical power to be applied to the flash memory device.
4. The flash memory device of claim 1 , wherein the flash memory die is tested a pre-determined number of times.
5. The flash memory device of claim 1 , wherein the at least one test program includes:
a first command to erase a block of the flash memory;
a second command to write data to the erased block;
a third command to read the written data as read data; and
a fourth command to compare the read data to the written data.
6. The flash memory device of claim 1 , wherein the flash controller includes an arithmetic logic unit (ALU) and wherein the at least one test program is executed entirely at the ALU.
7. A flash memory device comprising:
a flash memory residing on at least one flash memory die; and
a flash controller residing on a flash controller die separate from the at least one flash memory die, wherein:
the flash memory and the flash controller reside within, reside on, or are attached to, a common housing, and
the flash controller is configured to execute at least one test program to test the at least one flash memory die and to record at least some test results within the flash memory.
8. The flash memory device of claim 7 , wherein the at least some test results include a list indicating bad blocks within the flash memory.
9. The flash memory device of claim 7 , wherein the flash controller is configured to execute the at least one test program in response to a signal received from an external testing device.
10. The flash memory device of claim 7 , wherein the signal includes electrical power to be applied to the flash memory device.
11. The flash memory device of claim 7 , wherein the flash controller is configured to test a majority of memory cells of the flash memory.
12. The flash memory device of claim 7 , wherein the flash controller is configured to test at least seventy five percent of memory cells of the flash memory.
13. The flash memory device of claim 7 , wherein the flash controller is configured to test at least ninety percent of memory cells of the flash memory.
14. The flash memory device of claim 7 , wherein the at least one test program includes:
a first command to erase a block of the flash memory;
a second command to write data to the erased block;
a third command to read the written data as read data; and
a fourth command to compare the read data to the written data.
15. The flash memory device of claim 7 , wherein the flash controller includes an arithmetic logic unit (ALU) and wherein the at least one test program is executed entirely at the ALU.
16. A flash memory device comprising:
a flash memory residing on at least one flash memory die;
a flash controller residing on a flash controller die separate from the at least one flash memory die, wherein:
the flash memory. and the flash controller reside within a common housing; and
the flash controller is configured to execute at least one test program to effect bad block testing of a majority of memory cells of the flash memory.
17. The flash memory device of claim 16 , wherein the at least one test program is executed at the flash controller in response to an external electrical power signal received from an external testing device.
18. The flash memory device of claim 16 , wherein the at least one test program includes:
a first command to erase a block of the flash memory;
a second command to write data to the erased block;
a third command to read the written data as read data; and
a fourth command to compare the read data to the written data.
19. The flash memory device of claim 16 , wherein the flash controller includes an arithmetic logic unit (ALU) and wherein the at least one test program is executed entirely at the ALU.
20. The flash memory device of claim 16 , wherein after the at least one test program is executed, a flag at a memory cell of the flash memory is set to indicate that a bad block test associated with the at least one test program is complete.