Back diffusion suppression structures

1. An enhancement-mode III Nitride transistor comprising:

a substrate;

transition layers;

a buffer layer comprised of a III Nitride material;

a barrier layer comprised of a III Nitride material and having an Al fraction;

drain and source contacts;

a gate comprising:

a III Nitride layer containing at least one p-type dopant; and

a contact layer located over the III Nitride layer; and

a diffusion barrier layer disposed between the gate and the barrier layer, the diffusion barrier layer comprised of a III Nitride material and having an Al fraction, the entirety of the diffusion barrier layer being located over the barrier layer, wherein the Al fraction of the diffusion barrier layer is greater than the Al fraction of the barrier layer.

2. The transistor of claim 1 , wherein the buffer layer is comprised of In x Al y Ga 1-x-y N, where x+y<1.

3. The transistor of claim 1 , wherein the barrier layer is comprised of In x Al y Ga 1-x-y N of wider band gap than the buffer layer, where x+y<1.

4. The transistor of claim 1 , wherein the p-type dopant is selected from the group consisting of Mg, C, Ca, Fe, Cr, V, Mn, and Be.

5. The transistor of claim 3 , wherein the diffusion barrier layer is comprised of In x Al y Ga 1-x-y N, where x+y<1.

6. The transistor of claim 5 , wherein the III Nitride layer is an In x Al y Ga 1-x-y N layer, where x+y<1.

7. The transistor of claim 1 , further comprising a channel layer located between the diffusion barrier layer and the buffer layer.

8. The transistor of claim 1 , further comprising an additional diffusion barrier layer having an Al fraction, the entirety of the additional diffusion barrier layer being located below the barrier layer, wherein the Al fraction of the additional diffusion barrier layer is greater than the Al fraction of the barrier layer.

9. An enhancement-mode III Nitride transistor comprising:

a substrate;

transition layers;

a buffer layer comprised of a III Nitride material;

a barrier layer comprised of a III Nitride material;

drain and source contacts; and

a gate comprising:

a III Nitride layer, the III Nitride layer having a first region and a second region each having a p-dopant concentration, wherein the p-type dopant concentration of the first region is less than the p-type dopant concentration of the second region, the entirety of the III Nitride layer being located above the barrier layer; and

a contact layer located over the III Nitride layer.

10. The transistor of claim 9 , wherein the buffer layer is comprised of In x Al y Ga 1-x-y N, where x+y<1.

11. The transistor of claim 9 , wherein the barrier layer is comprised of In x Al y Ga 1-x-y N, where x+y<1.

12. The transistor of claim 9 , wherein the III Nitride layer further comprises a third region located above the second region, the third region having a p-type dopant concentration.

13. The transistor of claim 12 , wherein the p-type dopant concentration of the third region is greater than the p-type dopant concentration of the second region.

14. The transistor of claim 12 , wherein the p-type dopant concentration of the third region is less than the p-type dopant concentration of the second region.

15. The transistor of claim 12 , wherein the third region has an n-type dopant concentration.

16. The transistor of claim 15 , wherein the n-type dopant concentration of the third region is greater than the p-type dopant concentration of the third region near the top of the third region, and wherein the n-type dopant concentration is less than the p-type dopant concentration of the third region near the bottom of the third region.

17. The transistor of claim 15 , wherein the third region has an n-type dopant concentration that is less than the p-type dopant concentration of the third region.

18. The transistor of claim 9 , wherein the III Nitride layer has an undoped fourth region located below the first region.

19. The transistor of claim 9 , wherein the second region is located above the first region.