Vertical stacking of field effect transistor structures for logic gates
View Patent ↗Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.
1. A method for making independently controllable vertically stacked Field Effect Transistors (FETs) comprising:
forming, on a semiconductor substrate, a vertical structure comprising a first gate dielectric layer, a first conductor layer, a second dielectric layer, a second conductor layer, and a third dielectric layer;
implanting a first source/drain region having a first doping type, thereby creating a first source and a first drain for a first FET, the semiconductor substrate forming a first body for the first FET;
growing a first epitaxial layer having a second doping of the same type as the first doping type, thereby forming a second source and a second drain for a second FET;
growing a second epitaxial layer having a third doping of opposite type as the first doping type, thereby forming a second body for the second FET;
creating an isolation between the first source and the overlying first epitaxial layer;
connecting the first conductor layer to a first signal source;
connecting the second conductor layer to a second signal source.
2. The method of claim 1 further comprising connecting the first FET and the second FET in parallel.
3. The method of claim 1 further comprising connecting the first FET and the second FET in series.