Flat panel display
View Patent ↗A bottom gate thin film transistor (TFT), a flat panel display having the same, and a method of fabricating the same are disclosed. The TFT comprises a gate electrode disposed on a substrate, and a gate insulating layer disposed on the gate electrode. A semiconductor layer is disposed on the gate insulating layer and crossing over the gate electrode, and is crystallized by an MILC technique. An inter-insulating layer is disposed on the semiconductor layer and comprises source and drain contact holes which expose portions of the semiconductor layer. The source and drain contact holes are separated from at least one edge of the semiconductor layer crossing over the gate electrode. The semiconductor layer comprises conductive MIC regions corresponding to the exposed portions of the semiconductor layer in the source and drain contact holes.
1. A flat panel display comprising:
a light emitting element; and
a thin film transistor, electrically connected to the light emitting element, wherein the thin film transistor comprises:
a gate electrode disposed on a substrate,
a gate insulating layer disposed on the gate electrode,
a semiconductor layer disposed on the gate insulating layer and crossing over the gate electrode, wherein the semiconductor layer is crystallized by a metal induced lateral crystallization (MILC) technique,
an inter-insulating layer disposed on the semiconductor layer and comprising source and drain contact holes that expose portions of the semiconductor layer, wherein at least one edge of each of the source and drain contact holes of the inter-insulating layer overlaps the gate electrode,
source and drain electrodes disposed on the exposed portions of the semiconductor layer in the source and drain contact holes, respectively, and
a pixel electrode contacting one of the source electrode and the drain electrode,
wherein the semiconductor layer comprises metal induced crystallization (MIC) regions corresponding to the exposed portions of the semiconductor layer in the source and drain contact holes.
2. The flat panel display of claim 1 , wherein the MIC regions correspond to the exposed portions of the semiconductor layer in the source and drain contact holes.
3. The flat panel display of claim 1 , wherein the source and drain electrodes directly contact the exposed portions of the semiconductor layer.
4. The flat panel display of claim 1 , further comprising a passivation layer disposed between the source and drain electrodes and the pixel electrode, wherein the pixel electrode contacts one of the source electrode and the drain electrode through a via which penetrates the passivation layer.
5. The flat panel display of claim 1 , wherein the light emitting element comprises:
an organic functional layer disposed on the pixel electrode and having at least an emission layer; and
an opposite electrode disposed on the organic functional layer.
6. The flat panel display of claim 1 , wherein the semiconductor layer crosses over the gate electrode in a substantially orthogonal configuration.