Display device and manufacturing method thereof
View Patent ↗A display device includes a lower panel including a lower substrate and a pixel transistor formed on the lower substrate; and an upper panel facing the lower panel, and including an upper substrate, a sensing transistor formed on the upper substrate, and a readout transistor connected to the sensing transistor and transmitting a signal. The readout transistor includes a first lower gate electrode formed on the upper substrate, a first semiconductor layer formed on the first lower gate electrode and overlaps the first gate electrode, and a first source electrode and a first drain electrode disposed on the first semiconductor layer. The sensing transistor includes a light blocking film disposed on the upper substrate, a second lower gate electrode contacting the light blocking film on the light blocking film, a second semiconductor layer overlapping the light blocking film on the second lower gate electrode, a second source electrode and a second drain electrode formed on the second semiconductor layer, and a second upper gate electrode overlapping the second semiconductor layer on the second source electrode and the second drain electrode.
1. A display device, comprising:
a panel comprising an upper substrate and a lower substrate, and a pixel transistor formed on the lower substrate, wherein
the upper substrate is facing the lower substrate and an infrared ray sensing transistor and a readout transistor being connected to the infrared ray sensing transistor are provided on the upper substrate, and the readout transistor is provided to transmit a signal and wherein,
the readout transistor comprises a first lower gate electrode formed on the upper substrate, a first semiconductor layer overlapping the first lower gate electrode and formed on the first lower gate electrode, and a first source electrode and a first drain electrode formed on the first semiconductor layer and wherein,
the infrared ray sensing transistor comprises a light blocking film and a second lower gate electrode formed on the upper substrate, the second lower gate coupled to the light blocking film, a second semiconductor layer overlapping the light blocking film formed on the second lower gate electrode, a second source electrode and a second drain electrode formed on the second semiconductor layer, and a second upper gate electrode overlapping the second semiconductor layer formed on the second source electrode and the second drain electrode.
2. The display device of claim 1 , further comprising:
a first upper gate electrode overlapping the first semiconductor layer formed on the first source electrode and the first drain electrode.
3. The display device of claim 1 , further comprising
a first etching preventing layer formed between the first semiconductor layer, and the first source electrode and the first drain electrode.
4. The display device of claim 3 , wherein
the first etching preventing layer comprises one selected from Mo, Cr, MoAlMo, MoAl, IZO, or ITO.
5. The display device of claim 1 , wherein
the light blocking film is connected to the second upper gate electrode through the second lower gate electrode.
6. The display device of claim 1 , wherein
the thickness of the second semiconductor layer is in the range of about 3000 Åto 10,000 Å.
7. The display device of claim 1 , further comprising
a blocking insulating layer formed between the light blocking film and the second semiconductor layer and having a thickness of approximately 3000 Åto approximately 10,000 Å.
8. The display device of claim 1 , further comprising
a gate insulating layer formed between the second semiconductor layer and the second upper gate electrode and having a thickness of approximately 3000 Åto approximately 10,000 Å.
9. The display device of claim 1 , further comprising
a visible ray sensing transistor formed on the upper substrate and connected to the readout transistor,
wherein the visible ray sensing transistor comprises a third semiconductor layer positioned on the upper substrate and comprising amorphous silicon, a third source electrode and a third drain electrode positioned on the third semiconductor layer, and a third upper gate electrode overlapping the third semiconductor layer on the third source electrode and the third drain electrode.
10. The display device of claim 2 , further comprising:
a second etching preventing layer formed between the second semiconductor layer, and the second source electrode and the second drain electrode.