Display device and method of manufacturing the same

1. A display device comprising:

a display panel comprising:

a first pixel row comprising a first pixel connected to an (m+1)-th data line and one of an n-th gate line and an (n+1)-th gate line, where n and m are natural numbers, and a second pixel connected to an (m+2)-th data line and the remaining of the (n+1)-th gate line and the n-th gate line;

a second pixel row comprising a third pixel connected to an (n+2)-th gate line and an m-th data line, and a fourth pixel connected to an (n+3)-th gate line and the (m+1)-th data line;

a third pixel row comprising a fifth pixel connected to an (n+4)-th gate line and the (m+1)-th data line, and a sixth pixel connected to an (n+5)-th gate line and the (m+2)-th data line; and

a fourth pixel row comprising a seventh pixel connected to an (n+7)-th gate line and the m-th data line, and an eighth pixel connected to an (n+6)-th gate line and the (m+11)-th data line;

a data driving part which applies a data voltage having a first polarity with respect to a reference voltage to the (m+1)-th data line and which applies a data voltage having a second polarity with respect to the reference voltage to the (m+2)-th and m-th data lines; and

a gate driving part which sequentially applies a gate signal to the n-th, (n+1)-th, (n+4)-th, (n+5)-th, (n+2)-th, (n+3)-th, (n+6)-th and (n+7)-th gate lines in the above-listed order.

2. The display device of claim 1 , wherein the data driving part inverts polarities of data voltages applied to the m-th, (m+1)-th and (m+2)-th data lines on a frame basis.

3. The display device of claim 1 , wherein the first, third, fifth and seventh pixels are disposed symmetric to the second, fourth, sixth and eighth pixels, respectively, along the (m+1)-th data line.

4. The display device of claim 1 , wherein

the first, third, fifth and seventh pixels are disposed in a first pixel column line and display a first color, and

the second, fourth, sixth and eighth pixels are disposed in a second pixel column and display a second color different from the first color.

5. A display device comprising:

a display panel comprising:

a first pixel row comprising a first pixel connected to an (m+1)-th data line and one of an n-th gate line and an (n+1)-th gate line, where n and m are natural numbers, and a second pixel connected to an (m+2)-th data line and the remaining of the (n+1)-th gate line and the n-th gate-line;

a second pixel row comprising a third pixel connected to an (n+3)-th gate line and an m-th data line, and a fourth pixel connected to an (n+2)-th gate line and the (m+1)-th data line;

a third pixel row comprising a fifth pixel connected to an (n+4)-th gate line and (m+1)-th data and a sixth pixel connected to an (n+5)-th gate line and the (m+2)-th data line; and

a fourth pixel row comprising a seventh pixel connected to an (n+6)-th gate line and the m-th data line and an eighth pixel connected to an (n+7)-th gate line and the (m+1)-th data line;

the a data driving part which applies a data voltage having a first polarity with respect to a reference voltage to the (m+1)-th data line and which applies a data voltage having a second polarity with respect to the reference voltage to the m-th and (m+2)-th data lines; and

the a gate driving part which sequentially applies a gate signal to the n-th, (n+1)-th, (n+4)-th, (n+5)-th, (n+2)-th, (n+3)-th, (n+6)-th and (n+7)-th gate lines in the above-listed order.

6. The display device of claim 5 , wherein

the data driving part is disposed at a first side portion of the display panel, and

the gate driving part is disposed at a second side portion of the display panel.

7. A display device comprising:

a display panel comprising:

a first pixel row comprising a first pixel connected to an (m+1)-th data line and one of an n-th gate line and an (n+1)-th gate line, a second pixel connected to an (m+2)-th data line and the gate line connected to the first pixel, where n and m are natural numbers, a third pixel connected to the (m+2)-th data line and the remaining of the n-th gate line and the (n+1)-th gate line, and a fourth pixel connected to an (m+3)-th data line and the gate line connected to the third pixel;

a second pixel row comprising a fifth pixel connected to an (n+3)-th gate line and an m-th data line, a sixth pixel connected to the (n+3)-th gate line and the (m+1)-th data line, a seventh pixel connected to an (n+2)-th gate line and the (m+1)-th data line, and an eighth pixel connected to the (n+2)-th gate line and the (m+2)-th data line;

a third pixel row comprising a ninth pixel connected to an (n+4)-th gate line and an (m+1)-th data line, a tenth pixel connected to an (n+4)-th gate line and the (m+2)-th data line, an eleventh pixel connected to the (n+5)-th gate line and the (m+2)-th data line, and a twelfth pixel connected to the (n+5)-th gate line and the (m+3)-th data line; and

a fourth pixel row comprising a thirteenth pixel connected to an (n+6)-th gate line and the m-th data line, a fourteenth pixel connected to the (n+6)-th gate line and the (m+1)-th data line, a fifteenth pixel connected to an (n+7)-th gate line and the (m+1)-th data line, and a sixteenth pixel connected to the (n7)-th gate line and the (m+2)-th data line;

a data driving part which applies a first data voltage having a first polarity with respect to a reference voltage to the (m+1)-th data line, applies a second data voltage having a second polarity with respect to the reference voltage to the (m+2)-th and m-th data lines, and applies a third data voltage having the first polarity to the (m+3)-th data line; and

a gate driving part which sequentially applies a gate signal to the n-th, (n+1)-th, (n+4-th, (n+5)-th, (n+2)-th, (n+3)-th, (n+6)-th and (n+7)-th gate lines in the above-listed order.

8. The display device of claim 7 , wherein the data driving part inverts polarities of data voltages applied to the m-th, (m+1)-th and (m+2)-th data lines on a frame basis.

9. The display device of claim 8 , wherein

the first, fifth, ninth and thirteenth pixels are disposed symmetric to the second, sixth, tenth and fourteenth pixels, respectively, about the (m+1)-th data line, and

the third, seventh, eleventh and fifteenth pixels are disposed symmetric to the fourth, eighth, twelfth and sixteenth pixels, respectively, about the (m+2)-th data line.

10. The display device of claim 8 , wherein

the first, fifth, ninth and thirteenth pixels are disposed in a first pixel column and display a first color,

the second, sixth, tenth and fourteenth pixels are disposed in a second pixel column and display a second color different from the first color,

the third, seventh, eleventh and fifteenth pixels are disposed in a third pixel column and display a third color different from the first color and the second color, and

the fourth, eighth, twelfth and sixteenth pixels are disposed in a fourth pixel column and display the first color.

11. The display device of claim 10 , wherein

the gate driving part is disposed at a first side portion of the display panel, and

the data driving part is disposed at a second side portion of the display panel.

12. A display device comprising:

a display panel comprising:

a first pixel row comprising a first pixel connected to an (m+1)-th data line and one of an n-th gate line and an (n+1)-th gate line (‘n’ and ‘m’ are natural numbers), and a second pixel connected to an (m+2)-th data line and the remaining of the n-th gate line and the (n+1)-th gate line;

a second pixel row comprising a third pixel connected to the (m+1)-th data line and one of an (n+2)-th gate line and an (n+3)-th gate line, and a fourth pixel connected to the (m+2)-th data line and the remaining of the (n+2)-th gate line and the (n+3)-th gate line;

a third pixel row comprising a fifth pixel connected to the m-th data line and one of an (n+4)-th gate line and an (n+5)-th gate line and, and a sixth pixel connected to the (m+1)-th data line and the remaining of the (n+4)-th gate line and the (n+5)-th gate line; and

a fourth pixel row comprising a seventh pixel connected to the m-th data line and one of an (n+6)-th gate line and an (n+7)-th gate line, and an eighth pixel connected to the (m+1)-th data line and the remaining of the (n+6)-th gate line and the (n+7)-th gate line;

a data driving part which applies a data voltage having a first polarity with respect to a reference voltage to the (m+1)-th data line and applies a data voltage having a second polarity with respect to the reference voltage to the m-th and (m+2)-th data lines; and

a gate driving part which sequentially applies a gate signal to the n-th, (n+1)-th, (n+4)-th, (n+5)-th, (n+2)-th, (n+3)-th, (n+6)-th and (n+7)-th gate lines in the above-listed order.

13. The display device of claim 12 , wherein the data driving part inverts polarities of data voltages applied to the m-th, (m+1)-th and (m+2)-th data lines on a frame basis.

14. The display device of claim 13 , wherein the first, third, fifth and seventh pixels are disposed symmetric to the second, fourth, sixth and eighth pixels, respectively, about the (m+1)-th data line.

15. The display device of claim 13 , wherein

the first, third, fifth and seventh pixels are disposed in a first pixel column and display a first color, and

the second, fourth, sixth and eighth pixels are disposed in a second pixel column and display a second color different from the first color.

16. The display device of claim 15 , wherein

the data driving part is disposed at a first side portion of the display panel, and

the gate driving part is disposed at a second side portion of the display panel.

17. A method of manufacturing a display device, the method comprising:

forming a first pixel row comprising a first pixel connected to an (m+1)-th data line and one of an n-th gate line and an (n+1)-th gate line, where n and m are natural numbers, and a second pixel connected to an (m+2)-th data line and the remaining of the n-th gate line and the (n+1)-th gate line;

forming a second pixel row comprising a third pixel connected to an (n+2)-th gate line and an m-th data line, and a fourth pixel connected to an (n+3)-th gate line and the (m+1)-th data line;

forming a third pixel row comprising a fifth pixel connected to an (n+4)-th gate line and the (m+1)-th data line, and a sixth pixel connected to an (n+5)-th gate line and the (m+2)-th data line;

forming a fourth pixel row comprising a seventh pixel connected to an (n+7)-th gate line and the m-th data line, and an eighth pixel connected to an (n+6)-th gate line and the (m+1)-th data line;

forming a data driving part which applies a data voltage having a first polarity with respect to a reference voltage to the (m+1)-th data line and which applies a data voltage having a second polarity with respect to the reference voltage to the (m+2)-th and m-th data lines; and

forming a gate driving part which sequentially applies a gate signal to the n-th, (n+1)-th, (n+4)-th, (n+5)-th, (n+2)-th, (n+3)-th, (n+6-th and (n+7)-th gate lines in the above-listed order.