Thin film transistor array panel for x-ray detector

1. A thin film transistor array panel for an X-ray detector, the thin film transistor array panel comprising:

a gate wire formed on an insulating substrate and comprising a gate line and a gate electrode connected to the gate line;

a gate insulating layer formed on the gate wire;

a semiconductor layer formed on the gate insulating layer;

a data wire formed on the gate insulating layer and comprising:

a data line which intersects the gate line;

a source electrode connected to the data line and disposed on the semiconductor layer; and

a drain electrode disposed on the semiconductor layer separate from the source electrode;

a photo diode comprising:

a first electrode connected to the drain electrode;

a second electrode which faces the first electrode; and

a photo-conductive layer disposed between the first electrode and the second electrode;

a passivation layer disposed on the photodiode, the semiconductor layer, the data wire and the drain electrode, the passivation layer having a first contact hole which exposes the second electrode;

a bias signal line disposed on the passivation layer and connected to the second electrode through the first contact hole; and

a light blocking layer disposed directly on the passivation layer and the bias signal line to cover the photo diode.

2. The thin film transistor array panel of claim 1 , wherein the photo-conductive layer comprises a first amorphous silicon film comprising an N type impurity, a second amorphous silicon film disposed on the first amorphous silicon film and comprising intrinsic amorphous silicon, and a third amorphous silicon film disposed on the second amorphous silicon film and comprising a P type impurity.

3. The thin film transistor array panel of claim 2 , wherein the second electrode comprises transparent conductive oxide.

4. The thin film transistor array panel of claim 1 , further comprising an insulating layer interposed between the light blocking member and the bias signal line.

5. The thin film transistor array panel of claim 1 , wherein at least a portion of the bias signal line is disposed between the passivation layer and the light blocking layer.

6. The thin film transistor array panel of claim 5 , further comprising an insulating layer interposed between the light blocking member and the bias signal line.

7. The thin film transistor array panel of claim 6 , wherein the second electrode comprises transparent conductive oxide.

8. The thin film transistor array panel of claim 1 , wherein the bias signal line and the data line are extended along the same direction.

9. The thin film transistor array panel of claim 8 , further comprising an auxiliary data line connected to the data line through a second contact hole of the passivation layer which exposes the data line.

10. The thin film transistor array panel of claim 9 , wherein the photo-conductive layer comprises a first amorphous silicon film comprising an N type impurity, a second amorphous silicon film disposed on the first amorphous silicon film and comprising intrinsic amorphous silicon, and a third amorphous silicon film disposed on the second amorphous silicon film and comprising a P type impurity.

11. The thin film transistor array panel of claim 10 , wherein the second electrode comprises transparent conductive oxide.

12. The thin film transistor array panel of claim 11 , further comprising an insulating layer interposed between the light blocking member and the bias signal line.

13. The thin film transistor array panel of claim 9 , wherein at least a portion of the bias signal line is disposed between the passivation layer and the light blocking layer.