Non-volatile memory with power-saving multi-pass sensing
A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during sensing, which is included in read, and program/verify operations. A sensing verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, coupling of the memory cells to their bit lines are delayed during a precharge operation in order to reduced the cells' currents working against the precharge. In another aspect, a power-consuming precharge period is minimized by preemptively starting the sensing in a multi-pass sensing operation. High current cells not detected as a result of the premature sensing will be detected in a subsequent pass.
1. A nonvolatile memory, comprising:
a group of memory cells accessible by associated bit lines;
a group of sensing circuits for sensing the group of memory cells in parallel to determine the conduction currents of the memory cells relative to a first reference current;
a controller for controlling operations of the memory;
said controller controlling the sensing circuits in first and second pass sensing;
wherein:
the group of memory cells are set up and sensed in a first pass to identify those memory cells with conduction currents higher than a second reference current that is higher than the first reference current by a predetermined margin;
the identified higher current memory cells are turned off;
the remaining unidentified memory cells are set up and sensed in a second pass relative to the first reference current; and
the first pass further includes:
a period of setup being reduced by a first predetermined amount;
the predetermined margin by being increased by a second predetermined amount sufficient to accurately identify all memory cells with conduction currents higher than the second reference current; and
the first predetermined amount is such that the total power consumed by the first and second passes is reduced to a predetermined level.
2. The nonvolatile memory as in claim 1 , wherein said setting up is to set up the memory cell with voltages appropriate for sensing.
3. The nonvolatile memory as in claim 1 , wherein said controller controlling set up of the memory cells up includes controlling precharging of the associated bit lines.
4. The nonvolatile memory as in claim 1 , wherein a memory cell of the group is turned off by grounding its associated bit line.
5. The nonvolatile memory as in claim 1 , wherein said group of sensing circuits operates in a read operation to read the memory states programmed into said group of memory cells.
6. The nonvolatile memory as in claim 1 , wherein said group of sensing circuits operates in a program operation to verify if any of the memory cells has been programmed relative to the selected demarcation threshold voltage.
7. The nonvolatile memory as in claim 1 , wherein the group of nonvolatile memory cells is a part of a flash EEPROM.
8. The nonvolatile memory as in any one of claims 1 - 7 , wherein the nonvolatile memory cell of the group stores one bit of data.
9. The nonvolatile memory as in any one of claims 1 - 7 , wherein the nonvolatile memory cell of the group stores more than one bit of data.