Method and system for scalable video data width
Processing data samples may comprise partitioning the data samples in a first set of data bits and a second set of data bits and utilizing at least some of the first and second set of data bits while operating under a first condition. Only at least some of the first set of data bits may be utilized while operating under a second condition. The first condition may be a normal operating condition, while the second condition may be a performance restricted condition. The first set of data bits may be more significant bits and the second set of bits may be less significant bits. At least some of the first and second set of data bits may be utilized while bandwidth is available. Under the second condition, other values may be substituted for the data values from the second set that were not read in a read operation.
1. A method for processing data samples, the method comprising:
partitioning the data samples in a first set of data bits and a second set of data bits;
utilizing at least a portion of said first set of data bits and at least a portion of said second set of data bits while operating under a first condition, wherein said first condition is a higher performance operating condition; and
utilizing only at least a portion of said first set of data bits while operating under a second condition, wherein said second condition is a lower performance operating condition.
2. The method according to claim 1 , wherein said first set of data bits are more significant bits.
3. The method according to claim 1 , wherein said second set of data bits are less significant bits.
4. The method according to claim 1 , comprising utilizing said at least a portion of said first set of data bits and at least a portion of said second set of data bits while at least one of processor bandwidth and memory bandwidth are available.
5. The method according to claim 1 , comprising utilizing said at least a portion of said first set of data bits while bandwidth is limited.
6. The method according to claim 1 , comprising determining performance of a memory subsystem.
7. The method according to claim 6 , comprising choosing for use, said at least a portion of said first set of data bits along with said at least a portion of said second set of data bits, or said only at least a portion of said first set of data bits based on said determined performance of said memory subsystem.
8. The method according to claim 1 , comprising selecting said at least a portion of said first set of data bits along with said at least a portion of said second set of data bits, or said only at least a portion of said first set of data bits based on one of a plurality of varying levels of system performance.
9. The method according to claim 1 , comprising, for memory read operations, reading said at least a portion of said first set of data bits and said at least a portion of said second set of data bits while operating under said first condition.
10. The method according to claim 9 , comprising substituting during said second condition, internally generated bits for said second set of data bits that are read while operating under said first condition.
11. The method according to claim 1 , comprising, for memory read operations, reading said only at least a portion of said first set of data bits while operating under said second condition.
12. The method according to claim 1 , comprising, for memory write operations, writing said at least a portion of said first set of data bits and said at least a portion of said second set of data bits while operating under said first condition.
13. The method according to claim 1 , comprising, for memory write operations, writing said only at least a portion of said first set of data bits while operating under said second condition, wherein memory read operations and memory write operations occur under at least one of said first condition and said second condition.
14. The method according to claim 1 , wherein said first set of data bits forms a first data word.
15. The method according to claim 1 , wherein said second set of data bits forms a second data word.
16. A machine-readable storage having stored thereon, a computer program having at least one code section for processing data samples, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
partitioning the data samples in a first set of data bits and a second set of data bits;
utilizing at least a portion of said first set of data bits and at least a portion of said second set of data bits while operating under a first condition, wherein said first condition is a higher performance operating condition; and
utilizing only at least a portion of said first set of data bits while operating under a second condition, wherein said second condition is a lower performance operating condition.
17. The machine-readable storage according to claim 16 , wherein said first set of data bits are more significant bits.
18. The machine-readable storage according to claim 16 , wherein said second set of data bits are less significant bits.
19. The machine-readable storage according to claim 16 , comprising code for utilizing said at least a portion of said first set of data bits and at least a portion of said second set of data bits while at least one of processor bandwidth and memory bandwidth is available.
20. The machine-readable storage according to claim 16 , comprising code for utilizing said at least a portion of said first set of data bits while bandwidth is limited.
21. The machine-readable storage according to claim 16 , comprising code for determining performance of a memory subsystem.
22. The machine-readable storage according to claim 21 , comprising code for choosing for use, said at least a portion of said first set of data bits along with said at least a portion of said second set of data bits, or said only at least a portion of said first set of data bits based on said determined performance of said memory subsystem.
23. The machine-readable storage according to claim 16 , comprising code for selecting said at least a portion of said first set of data bits along with said at least a portion of said second set of data bits, or said only at least a portion of said first set of data bits based on one of a plurality of varying levels of system performance.
24. The machine-readable storage according to claim 16 , comprising code for memory reading operations that reads said at least a portion of said first set of data bits and said at least a portion of said second set of data bits while operating under said first condition.
25. The machine-readable storage according to claim 24 , comprising code for substituting during said second condition, internally generated bits for said second set of data bits that are read while operating under said first condition.
26. The machine-readable storage according to claim 16 , comprising code for memory reading operations that reads said only at least a portion of said first set of data bits while operating under said second condition.
27. The machine-readable storage according to claim 16 , comprising code for memory writing operations that writes said at least a portion of said first set of data bits and said at least a portion of said second set of data bits while operating under said first condition.
28. The machine-readable storage according to claim 16 , comprising code for memory writing operations that writes said only at least a portion of
said first set of data bits while operating under said second condition, wherein memory reading operations and memory writing operations occur under at least one of said first condition and said second condition.
29. The machine-readable storage according to claim 16 , wherein said first set of data bits forms a first data word.
30. The machine-readable storage according to claim 16 , wherein said second set of data bits forms a second data word.
31. A system for processing data samples, the system comprising:
at least one processor operable to partition the data samples in a first set of data bits and a second set of data bits;
said at least one processor operable to utilize at least a portion of said first set of data bits and at least a portion of said second set of data bits while operating under a first condition, wherein said first condition is a higher performance operating condition; and
said at least one processor operable to utilize only at least a portion of said first set of data bits while operating under a second condition, wherein said second condition is a lower performance operating condition.
32. The system according to claim 31 , wherein said first set of data bits are more significant bits.
33. The system according to claim 31 , wherein said second set of data bits are less significant bits.
34. The system according to claim 31 , wherein said at least one processor is operable to utilize said at least a portion of said first set of data bits and at least a portion of said second set of data bits while at least one of processor bandwidth and memory bandwidth are available.
35. The system according to claim 31 , wherein said at least one processor is operable to utilize said at least a portion of said first set of data bits while bandwidth is limited.
36. The system according to claim 31 , wherein said at least one processor is operable to determine performance of a memory subsystem.
37. The system according to claim 36 , wherein said at least one processor is operable to choose for use, said at least a portion of said first set of data bits along with said at least a portion of said second set of data bits, or said only at least a portion of said first set of data bits based on said determined performance of said memory subsystem.
38. The system according to claim 31 , wherein said at least one processor is operable to select said at least a portion of said first set of data bits along with said at least a portion of said second set of data bits, or said only at least a portion of said first set of data bits based on one of a plurality of varying levels of system performance.
39. The system according to claim 31 , wherein said at least one processor is operable to, for memory read operations, read said at least a portion of said first set of data bits and said at least a portion of said second set of data bits while operating under said first condition.
40. The system according to claim 39 , wherein said at least one processor is operable to substitute during said second condition, internally generated bits for said second set of data bits that are read while operating under said first condition.
41. The system according to claim 31 , wherein said at least one processor is operable to, for memory read operations, read said only at least a portion of said first set of data bits while operating under said second condition.
42. The system according to claim 31 , wherein said at least one processor is operable to, for memory write operations, write said at least a portion of said first set of data bits and said at least a portion of said second set of data bits while operating under said first condition.
43. The system according to claim 31 , wherein said at least one processor is operable to, for memory write operations, write said only at least a portion of said first set of data bits while operating under said second condition, wherein memory read operations and memory write operations occur under at least one of said first condition and said second condition.
44. The system according to claim 31 , wherein said first set of data bits forms a first data word.
45. The system according to claim 31 , wherein said second set of data bits forms a second data word.