Granted Patent B2

US 9,020,781 · App. 12/764,051 · Granted Apr 28, 2015

Abstract

Claims (42)

1. A method comprising:

detecting one or more input signals associated with one or more memory modules by using a differential pair of transistors configuration housed on a respective memory module of the one or more memory modules, the differential pair of transistors configuration being coupled between a power supply and ground potential and coupled to an output node;

generating, by using the differential pair of transistors configuration, one or more output signals based on at least a subset of the detected one or more input signals;

using a voltage divider coupled to a base of a second transistor of the differential pair and operable to provide as a reference signal a programmable reference voltage between zero and an operating voltage of the respective memory module, and a first transistor of the differential pair coupled to the power supply;

using a first resistor configurable to be coupled to the base of the second transistor and the voltage divider;

using a second resistor configurable to be coupled to the base of the second transistor, and further coupled to a preselected reference voltage, wherein the first resistor is installed when the programmable reference voltage is applied; and wherein the second resistor is installed when the preselected reference voltage is applied;

routing the one or more output signals to an area external to the associated one or more memory modules; and

generating a first parameter information based on the one or more output signals, wherein the first parameter information is indicative of activity on the associated one or more memory modules, and wherein the area external to the associated one or more memory modules is only for enabling display of the first parameter information.

2. The method of claim 1 , wherein the one or more input signals comprise one or more chip select signals of the associated one or more memory modules.

3. The method of claim 1 , wherein generating the one or more output signals based on the at least a subset of the one or more input signals comprises generating one or more buffered chip select signals.

4. The method of claim 1 , wherein the one or more output signals are buffered by a transistor configured as an emitter follower.

5. The method of claim 1 , further comprising comparing the one or more input signals to a threshold value, and generating one or more inverted output signals based on the comparison.

6. The method of claim 1 , further comprising:

detecting a subset of other signals corresponding to N parameter information of the associated one or more memory modules;

generating at least a subset of N parameter information based on the subset of the other signals, wherein the N parameter information includes: temperature measurement data, a memory module clock signal, and power supply information for the one or more memory modules; and

displaying the at least a subset of N parameter information.

7. The method of claim 1 , further comprising displaying the first parameter information associated with the one or more memory modules on at least one accessory device.

8. The method of claim 1 , wherein generating the one or more output signals is achieved off the one or more memory modules.

9. The method of claim 1 , further comprising:

aggregating the first parameter information from a subset of the one or more memory modules; and

displaying the aggregated first parameter information of the subset of the one or more memory modules.

10. The method of claim 1 , wherein routing the one or more output signals to an area external to the associated one or more memory modules comprises routing the one or more output signals wirelessly.

11. A device associated with one or more memory modules comprising:

a power supply and ground potential;

at least one connector node; and

at least one differential pair of transistors coupled between the power supply and ground potential, the at least one differential pair of transistors having an output coupled to the at least one connector node,

wherein the at least one differential pair of transistors is configured to receive one or more input signals from the one or more memory modules and operable to generate one or more output signals based on at least a subset of the one or more input signals, and to provide the one or more output signals to the at least one connector node, and

wherein the at least one connector node is configured to route the one or more output signals off the one or more memory modules for display purposes only;

a voltage divider coupled to a base of a second transistor of the differential pair and operable to provide as a reference signal a programmable reference voltage between zero and an operating voltage of the memory module, and a first transistor of the differential pair coupled to the power supply;

a first resistor configurable to be coupled to the base of the second transistor and the voltage divider; and

a second resistor configurable to be coupled to the base of the second transistor, and further coupled to a preselected reference voltage, wherein the first resistor is installed when the programmable reference voltage is applied, and wherein the second resistor is installed when the preselected reference voltage is applied.

12. The device of claim 11 , wherein the one or more input signals correspond to size or number of chips on the one or more memory modules.

13. The device of claim 11 , further comprising a plurality of connector nodes for receiving a subset of the one or more output signals.

14. The device of claim 13 , further comprising at least one accessory device coupled to at least a subset of the plurality of connector nodes, the at least one accessory device configured to receive the one or more output signals at the at least a subset of the plurality of connector nodes, and operable to display a representation of the received one or more output signals.

15. The device of claim 11 , further comprising at least one of:

a temperature measuring device coupled to the at least one connector node, the temperature measuring device being operable to measure the temperature of the one or more memory modules; and

a clock divider circuit coupled to the at least one connector node, the clock divider circuit being operable to divide a received memory module clock signal.

16. The device of claim 11 , further comprising at least one accessory device coupled to the at least one connector node, the at least one accessory device being configured to receive information including at least a subset of: temperature measurement data, the one or more output signals, a memory module clock signal, and power supply information from the one or more modules.

17. The device of claim 16 , wherein the accessory device is a computing device associated with the one or more memory modules via at least one host interface.

18. The device of claim 16 , further comprising a display device coupled to the at least one accessory device, and configured to display a representation of the information received by the at least one accessory device.

19. The device of claim 16 , further comprising at least one computing device associated with the at least one accessory device via at least one host interface, the at least one computing device operable to process at least a subset of: temperature measurement data, the one or more output signals, a memory module clock signal, and power supply information of the one or more modules.

20. The device of claim 11 , wherein the at least one differential pair of transistors comprises an emitter follower.

Assignments (8)