CML output driver
View Patent ↗An integrated circuit (IC) for driving a light emitting semiconductor device is provided. The IC includes an input stage configured to receive a first input signal with a first differential pair of bipolar transistors and a second input signal with a second differential pair of bipolar transistors and to provide a pre-driver output signal being a superposition of the first input signal and the second input signal and an output stage including a third differential pair of bipolar transistors for receiving the pre-driver output signal of the input stage and for driving the light emitting semiconductor device in response to the pre-driver output signal, wherein the IC is configured to pre-distort the pre-driver output signal of the input stage so as to compensate a signal distortion of the output stage.
1. A system, comprising:
a pre-distortion input buffer circuit that receives a drive signal and generates differential voltages VIN 1 and VIN 2 that when combined by superposition provide output signal pre-distortion; and
a current mode logic (CML) output circuit configured to receive VIN 1 and VIN 2 , and perform superposition to generate an output voltage VOUT with output signal pre-distortion, including:
a pre-driver stage configured to receive VIN 1 and VIN 2 , and to generate a pre-driver output voltage VIN 3 with pre-distortion corresponding to a superposition of VIN 1 and VIN 2 , and including:
a first differential pair of bipolar transistors having a first pair of differential input terminals coupled to receive VIN 1 , and having a first pair of differential output nodes; and
a second differential pair of bipolar transistors having a second pair of differential input terminals coupled to receive VIN 2 , and having a second pair of differential output nodes;
the first and second differential output nodes both connected to respective pre-driver differential output terminals; and
first and second pre-driver load transistors coupled between a supply rail, and respective ones of the first differential output nodes, and respective ones of the second differential output nodes;
the first differential pair of transistors generating a corresponding output current IOUT 1 linearly related to VIN 1 ;
the second differential pair of transistors generating a corresponding output current IOUT 2 linearly related to VIN 2 ; and
the first and second pre-driver load transistors generating at the pre-driver output terminals the pre-driver output voltage VIN 3 corresponding to a pre-driver output current IOUT,PRE that is a superposition of IOUT 1 and IOUT 2 ; and
an CML output stage configured to receive VIN 3 , and to generate VOUT with output pre-distortion, and including
a third differential pair of bipolar transistors having a pair of input terminals connected to the pre-driver output terminals to receive VIN 3 , and having a third pair of differential output nodes connected to output stage differential output terminals OUTp and OUTn;
first and second output load components coupled between a supply rail, and respective ones of the third differential output nodes;
the third differential pair of transistors, the first and second pre-driver load transistors, and the first and second output load components configured such the third differential pair of transistors generates an output current IOUT corresponding to a linear conversion of the pre-driver output current IOUT,PRE, so that the output stage generates VOUT at the differential output stage terminals OUTp and OUTn as a linear function of VIN 1 and VIN 2 , with output signal pre-distortion.
2. The system of claim 1 , wherein
the first differential pair of transistors are each coupled to respective first degeneration resistors; and
the second differential pair of transistors are each coupled to respective second degeneration resistors.
3. The system of claim 1 , wherein the first and second pre-driver load transistors are one of first and second diode-coupled bi-polar transistors, and first and second common-base bi-polar transistors.
4. The system of claim 1 , further comprising
a first buffer amplifier coupled at an input to respective ones of the first and second differential output nodes, and coupled at an output to a respective one of the pre-driver output terminals; and
a second buffer amplifier coupled at an input to respective other ones of the first and second differential output nodes, and coupled at an output to a respective other one of the pre-driver output terminals;
such that the first and second buffer amplifiers receive VIN 3 , and generate a corresponding buffered VIN 4 ; and
such that the CML output stage receives the buffered voltage VIN 4 .
5. The system of claim 1 , wherein the pre-driver stage first and second load transistors are of the same type as the CML output stage third differential pair transistors.
6. The system of claim 1 , wherein the pre-distortion input buffer circuit comprises:
a delay circuit that receives the drive signal, and generates a delayed differential voltage VIN 1 ; and
a pulse generation circuit that that receives the drive signal, and generates the differential voltage VIN 2 as pre-distortion pulses.
7. The system of claim 1 , wherein the output voltage VOUT with signal pre-distortion is output to one or more light emitting semiconductor devices.
8. An apparatus suitable for generating an output voltage with output signal pre-distortion, comprising:
a current mode logic (CML) output circuit including a CML pre-driver stage, and a CML output stage, the CML output circuit configured to receive differential voltages VIN 1 and VIN 2 , and perform superposition to generate an output voltage VOUT with output signal pre-distortion;
the CML pre-driver stage configured to receive VIN 1 and VIN 2 , and to generate a pre-driver output voltage VIN 3 with pre-distortion corresponding to a superposition of VIN 1 and VIN 2 , and including:
a first differential pair of bipolar transistors having a first pair of differential input terminals coupled to receive VIN 1 , and having a first pair of differential output nodes; and
a second differential pair of bipolar transistors having a second pair of differential input terminals coupled to receive VIN 2 , and having a second pair of differential output nodes;
the first and second differential output nodes both connected to respective pre-driver differential output terminals; and
first and second pre-driver load transistors coupled between a supply rail, and respective ones of the first differential output nodes, and respective ones of the second differential output nodes;
the first differential pair of transistors generating a corresponding output current IOUT 1 linearly related to VIN 1 ;
the second differential pair of transistors generating a corresponding output current IOUT 2 linearly related to VIN 2 ; and
the first and second pre-driver load transistors generating at the pre-driver output terminals the pre-driver output voltage VIN 3 corresponding to a pre-driver output current IOUT,PRE that is a superposition of IOUT 1 and IOUT 2 ; and
the CML output stage configured to receive VIN 3 , and to generate VOUT with output pre-distortion, and including
a third differential pair of bipolar transistors having a pair of input terminals connected to the pre-driver output terminals to receive VIN 3 , and having a third pair of differential output nodes connected to output stage differential output terminals OUTp and OUTn;
first and second output load components coupled between a supply rail, and respective ones of the third differential output nodes;
the third differential pair of transistors, the first and second pre-driver load transistors, and the first and second output load components configured such the third differential pair of transistors generates an output current IOUT corresponding to a linear conversion of the pre-driver output current IOUT,PRE, so that the output stage generates VOUT at the differential output stage terminals OUTp and OUTn as a linear function of VIN 1 and VIN 2 , with output signal pre-distortion.
9. The apparatus of claim 8 , wherein
the first differential pair of transistors are each coupled to respective first degeneration resistors; and
the second differential pair of transistors are each coupled to respective second degeneration resistors.
10. The apparatus of claim 8 , wherein the first and second pre-driver load transistors are one of first and second diode-coupled bi-polar transistors, and first and second common-base bi-polar transistors.
11. The apparatus of claim 8 , further comprising
a first buffer amplifier coupled at an input to respective ones of the first and second differential output nodes, and coupled at an output to a respective one of the pre-driver output terminals; and
a second buffer amplifier coupled at an input to respective other ones of the first and second differential output nodes, and coupled at an output to a respective other one of the pre-driver output terminals;
such that the first and second buffer amplifiers receive VIN 3 , and generate a corresponding buffered VIN 4 ; and
such that the CML output stage receives the buffered voltage VIN 4 .
12. The apparatus of claim 8 , wherein the pre-driver stage first and second load transistors are of the same type as the CML output stage third differential pair transistors.
13. The apparatus of claim 8 , wherein the pre-distortion input buffer circuit comprises:
a delay circuit that receives the drive signal, and generates a delayed differential voltage VIN 1 ; and
a pulse generation circuit that that receives the drive signal, and generates the differential voltage VIN 2 as pre-distortion pulses.
14. The apparatus of claim 8 , wherein the output voltage VOUT with signal pre-distortion is output to one or more light emitting semiconductor devices.