Dual mode test access port method and apparatus
Two common varieties of test interfaces exist for ICs and/or cores, the IEEE 1149.1 Test Access Port (TAP) interface and internal scan test ports. The TAP serves as a serial communication port for accessing a variety of circuitry including; IEEE 1149.1 boundary scan circuitry, built in self test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation/debug circuitry, and IEEE P1532 in-system programming circuitry. Internal scan test ports serve as a serial communication port for primarily accessing internal scan circuitry within ICs and cores. Today, the TAP and internal scan test ports are typically viewed as being separate test interfaces, each utilizing different IC pins and/or core terminals. The need for different IC pins and/or core terminals is overcome by an interface in accordance with the disclosure that allows the TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core terminals. Further, this interface allows merged TAP and scan test port interfaces to be selected individually or in groups.
1. An integrated circuit comprising:
A. functional circuitry having data input leads and data output leads;
B. a serial data input lead, a serial data output lead, a select input lead, and a clock input lead;
C. test access port circuitry having a test data input lead connected with the serial data input lead, a test data output lead connected with the serial data output lead, a test mode select lead coupled with the select input lead, a test clock lead connected with the clock input lead, scan circuitry control output leads that include a capture select select lead and a capture-DR lead, and a data register connected in series between the test data input lead and the test data output lead;
D. scan test port circuitry having a scan input lead connected to the serial data input lead, a scan output lead coupled with the serial data output lead, a scan enable input lead, a capture select input lead, a scan clock input lead, and a scan register connected between the scan input lead and the scan output lead, the scan register having functional data output and input leads connected to the functional circuitry data input and output leads;
E. connection circuitry coupling the scan test port circuitry to the test access port circuitry, the connection circuitry having inputs connected to the scan circuitry control output leads, the select input lead, and the clock input lead, the connection circuitry having outputs connected to the scan enable input lead, the capture select input lead, and the scan clock input lead, the connection circuitry including a first multiplexer having a control input connected with the capture select select lead, an input connected with the select input lead, an input connected with the capture-DR lead, and an output connected with the capture select input lead.
2. The integrated circuit of claim 1 in which the test access port circuitry includes:
i. TAP controller circuitry having a test mode select input lead selectively coupled to the select lead, a test clock input lead connected to the clock lead, data register control leads, instruction register control leads, a multiplexer select output lead, and a buffer enable output lead,
ii. a data register having a data input connected to the test data input lead and having a data output,
iii. an instruction register having a data input connected to the test data input, a data output, and scan circuitry control output leads,
iv. a multiplexer having a first input connected to the data output of the data register, a second input connected to the data output of the instruction register, a control input connected with the multiplexer select output lead, and a data output, and
v. an output data buffer having an input coupled to the data output of the multiplexer, a control input connected with the buffer enable output lead, and an output connected to the test data output lead.
3. The integrated circuit of claim 1 in which the test access port circuitry includes TAP controller circuitry having outputs and the capture-DR lead of the scan circuitry control output leads connects with an output of the TAP controller circuitry.