IP Library Granted Patent US 8,516,431
Granted Patent B2
US 8,516,431 · App. 12/764,481 · Granted Aug 20, 2013

Rule check system, design rule check method and design rule check program

Inventor: Takahiro Yaguchi (Tokyo, JP)
Assignee: NEC Informatec Systems, Ltd.
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Quick Facts
Patent No.
US 8,516,431
App. No.
12/764,481
Granted
Aug 20, 2013
Kind
B2
Abstract

A design rule check system includes: a design rule check unit that performs a design rule checks on wiring information which indicates a wiring pattern of a net on the basis of a design rule which includes a constraint condition of a wiring pattern; and a screening processing unit which generates information about an error for each clock frequency of each net based on a result of the design rule check and outputs the information to an indicating device.

Claims (19)

1. A design rule check system comprising:

a design rule check unit that performs a design rule check on the basis of wiring information relating to a wiring pattern of each net and a design rule which includes a constraint condition of a wiring pattern; and

a screening processing unit which generates error information about an error in said each net for each combination of design rule check items and operating frequencies of each net based on a result of said design rule check and outputs said error information to an indicating device;

wherein said screening processing unit outputs error list data of nets which have become an error about a selected combination of the check item of said design rule and operating frequency of said each net;

wherein said screening processing unit selects a combination of check items of said design rule and operating frequencies of said each net based on error selection default information which indicates a combination with a high priority of error correction among combinations of check items of said design rule and operating frequencies of said each net;

wherein said error selection default information is a combination with a high effect of EMI reduction among combinations of check items of said design rule and operating frequencies of said each net.

2. A method of a design rule check system comprising:

performing, at an information processing apparatus, a design rule check on the basis of wiring information a wiring pattern of each net and a design rule which includes a constraint condition of a wiring pattern;

generating, at the information processing apparatus, error information about an error in said each net for each combination of design rule check items and operating frequencies of said each net based on a result of said design rule check;

outputting, from the information processing apparatus, said error information to an indicating device;

outputting error list data of nets which have become an error about said selected combination of the check item of said design rule and operating frequency of said each net; and

selecting a combination of check items of said design rule and operating frequencies of said each net based on error selection default information which indicates a combination with a high priority of error correction among combinations of check items of said design rule and operating frequencies of said each net;

wherein said error selection default information is a combination with a high effect of EMI reduction among combinations of check items of said design rule and operating frequencies of said each net.

3. A non-transitory computer-readable medium storing a program which makes a computer function as:

a design rule check unit that performs a design rule check on the basis of wiring information a wiring pattern of each net and a design rule which includes a constraint condition of said wiring pattern; and

a screening processing unit which generates error information about an error in said each net for each combination of design rule check items and operating frequencies of said each net based on a result of said design rule check and outputs said error information to an indicating device;

wherein said medium stores a program which makes said computer carry out processing of outputting error list data of nets which have become an error about a selected combination of check items of said design rule and operating frequencies of said each net;

wherein said medium stores a program which makes said computer carry out processing of selecting a combination of check items of said design rule and operating frequencies of said each net based on error selection default information which indicates a combination with a high priority of error correction among combinations of check items of said design rule and operating frequencies of said each net;

wherein said error selection default information is a combination with a high effect of EMI reduction among combinations of check items of said design rule and operating frequencies of said each net.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Jun 26, 2017
From: NEC INFORMATEC SYSTEMS, LTD.; NEC SOFT, LTD.
To: NEC SOLUTION INNOVATORS, LTD.
Reel/Frame 042817/0787 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2010
From: YAGUCHI, TAKAHIRO
To: NEC INFORMATEC SYSTEMS, LTD.
Reel/Frame 024266/0262 →
Priority Claims (1)
JP 2009-104748 · Apr 23, 2009 · national
Continuity (1)
Related Publication 20100275172A1 · Oct 28, 2010