Integrated circuit device having ground open detection circuit
View Patent ↗An integrated circuit device includes a chip having a power supply terminal, a ground terminal, an input terminal, and an internal circuit formed therein. The chip comprises: a unidirectional device disposed between the input terminal and the ground terminal and directed from the ground terminal to the input terminal; and a ground open detection circuit including a first transistor having the gate connected to the input terminal and the source and the drain connected between the power supply terminal and the ground terminal, a second transistor having the gate connected to the ground terminal and the source and the drain connected between the power supply terminal and the ground terminal, and a comparator for comparing potentials of nodes respectively between drains of the first and second transistors and the power supply terminal, and for outputting a ground open detection signal.
1. An integrated circuit device comprising:
a chip having a power supply terminal, a ground terminal, an input terminal and an internal circuit,
wherein the chip comprises:
a unidirectional device disposed between the input terminal and the ground terminal and directed from the ground terminal to the input terminal; and
a ground open detection circuit including a first transistor having the gate connected to the input terminal and the source and the drain connected between the power supply terminal and the ground terminal, a second transistor having the gate connected to the ground terminal and the source and the drain connected between the power supply terminal and the ground terminal, and a comparator for comparing potentials of nodes respectively between drains of the first and second transistors and the power supply terminal, and for outputting a ground open detection signal indicative of an open condition in which the ground terminal of the chip is not connected to an external ground terminal.
2. The integrated circuit device according to claim 1 ,
wherein a first relationship between the resistance of the first transistor and the resistance of the second transistor when an identical potential is supplied to each gate of the first transistor and the second transistor is different from a second relationship between the resistance of the first transistor and the resistance of the second transistor when the gate potential of the second transistor is higher than the gate potential of the first transistor.
3. The integrated circuit device according to claim 2 ,
wherein, when an identical potential is supplied to each gate of the first transistor and the second transistor, the resistance of the first transistor is greater than the resistance of the second transistor, while when the gate potential of the second transistor is higher than the gate potential of the first transistor, the resistance of the first transistor is smaller than the resistance of the second transistor.
4. The integrated circuit device according to claim 3 ,
wherein the first and second transistors are P-channel transistors, and
wherein current source circuits are provided between the sources of the first and second transistors and the power supply terminal, respectively.
5. The integrated circuit device according to claim 2 ,
wherein, when an identical potential is supplied to each gate of the first transistor and the second transistor, the resistance of the first transistor is equal to the resistance of the second transistor, while when the gate potential of the second transistor is higher than the gate potential of the first transistor, the resistance of the first transistor is smaller than the resistance of the second transistor.
6. The integrated circuit device according to claim 5 ,
wherein the first and second transistors are P-channel transistors, and
wherein first and third resistors are provided between the power supply terminal and the source of the first transistor, and second and fourth resistors are provided between the power supply terminal and the source of the second transistor, and the third resistor has a greater resistance than the fourth resistor, and
wherein the comparator compares a connection node of the first and third resistors with a connection node of the second and fourth resistors.
7. The integrated circuit device according to claim 5 ,
wherein the first and second transistors are P-channel transistors, and
wherein a fifth resistor is provided between the power supply terminal and the source of the first transistor, and a sixth resistor is provided between the power supply terminal and the source of the second transistor, and the fifth resistor has a smaller resistance than the sixth resistor, and
wherein the comparator compares between source nodes of the first and second transistors.
8. The integrated circuit device according to claim 1 or 2 , wherein, to the input terminal, a ground potential is supplied.
9. The integrated circuit device according to claim 1 or 2 ,
wherein, to the input terminal, a clock signal having a power supply potential and a ground potential repeated alternately is supplied.
10. An integrated circuit device comprising:
a chip having a power supply terminal, a ground terminal and an input terminal, and an internal circuit,
wherein the chip comprises:
a first unidirectional device disposed between the input terminal and the ground terminal and directed from the ground terminal to the input terminal;
a second unidirectional device disposed between the input terminal and the power supply terminal and directed from the input terminal to the power supply terminal;
in case of a ground open condition in which the ground terminal of the chip is not connected to an external ground terminal, a ground open detection circuit for detecting a potential difference between the input terminal and the ground terminal of the chip, and for outputting a ground open detection signal; and
in case of a power supply open condition in which the power supply terminal of the chip is not connected to an external power supply terminal, a power-supply open detection circuit for detecting a potential difference between the input terminal and the power supply terminal of the chip, and for outputting a power-supply open detection signal,
wherein, to the input terminal, a clock signal having a power supply potential and a ground potential repeated alternately is supplied.
11. The integrated circuit device according to claim 10 ,
wherein the ground open detection circuit includes a first transistor having the gate connected to the input terminal and the source and the drain connected between the power supply terminal and the ground terminal, a second transistor having the gate connected to the ground terminal and the source and the drain connected between the power supply terminal and the ground terminal, and a comparator for comparing potentials of nodes respectively between drains of the first and second transistors and the power supply terminal, and for outputting a ground open detection signal indicative of the ground open condition.
12. The integrated circuit device according to claim 11 ,
wherein a first relationship between the resistance of the first transistor and the resistance of the second transistor when an identical potential is supplied to each gate of the first transistor and the second transistor is different from a second relationship between the resistance of the first transistor and the resistance of the second transistor when the gate potential of the second transistor is higher than the gate potential of the first transistor.