Semiconductor device with shallow trench isolation
View Patent ↗To provide a semiconductor device provided with an element isolation structure capable of hindering an adverse effect on electric characteristics of a semiconductor element, and a method of manufacturing the same. The thickness of a first silicon oxide film left in a shallow trench isolation having a relatively narrow width is thinner than the first silicon oxide film left in a shallow trench isolation having a relatively wide width. A second silicon oxide film (an upper layer) having a relatively high compressive stress by an HDP-CVD method is more thickly laminated over the first silicon oxide film in a lower layer by a thinned thickness of the first silicon oxide film. The compressive stress of an element isolation oxide film finally formed in a shallow trench isolation having a relatively narrow width is more enhanced.
1. A semiconductor device comprising:
a first shallow trench isolation having a prescribed depth and a first width so as to surround a first region in the semiconductor substrate;
a second shallow trench isolation having a prescribed depth and a second width narrower than the first width so as to surround a second region in the semiconductor substrate;
a first element isolation insulating film embedded in the first shallow trench isolation; and
a second element isolation insulating film embedded in the second shallow trench isolation, wherein:
the second element isolation insulating film includes: a first insulating film having a prescribed density; and a second insulating film having a density higher than the density of the first insulating film;
in the second shallow trench isolation, the first insulating film and the second insulating film are embedded so that the second insulating film is stacked over the first insulating film; and
the first element isolation insulating film includes the first insulating film and does not include the second insulating film.
2. The semiconductor device according to claim 1 , further comprising
a third shallow trench isolation having a prescribed depth and a third width narrower than the second width so as to surround a third region in the semiconductor substrate, wherein;
the second element isolation insulating film is embedded in the third shallow trench isolation;
in the third shallow trench isolation, the first insulating film and the second insulating film are embedded so that the second insulating film is stacked over the first insulating film; and
the second insulating film embedded in the third shallow trench isolation is formed thicker than the second insulating film embedded in the second shallow trench isolation.
3. The semiconductor device according to claim 1 , wherein the wet etching rate of the second insulating film for a prescribed wet etching liquid is lower than that of the first insulating film for the wet etching liquid.
4. The semiconductor device according to claim 1 , wherein the contraction percentage of the second insulating film by a prescribed heat treatment is smaller than that of the first insulating film by the heat treatment.
5. The semiconductor device according to claim 1 , wherein the first insulating film is a silicon oxide film by coating or O 3 -TEOS, and the second insulating film is a silicon oxide film by a high density plasma chemical vapor deposition method.
6. The semiconductor device according to claim 1 , further comprising: a first transistor formed in the first region and including a first gate electrode; a second transistor formed in the second region and including a second gate electrode; and a third transistor formed in a third region and including a third gate electrode.
7. A semiconductor device comprising:
a first shallow trench isolation having a prescribed depth and a first width so as to surround a first region in the semiconductor substrate;
a second shallow trench isolation having a prescribed depth and a second width narrower than the first width so as to surround a second region in the semiconductor substrate;
a third shallow trench isolation having a prescribed depth and a third width narrower than the second width so as to surround a third region in the semiconductor substrate;
a first element isolation insulating film embedded in the first shallow trench isolation;
a second element isolation insulating film embedded in the second shallow trench isolation and the third shallow trench isolation, wherein:
the first element isolation insulating film includes the first insulating film;
the second element isolation insulating film includes: a first insulating film having a prescribed density; and a second insulating film having a density higher than the density of the first insulating film;
in the second shallow trench isolation, the first insulating film and the second insulating film are embedded so that the second insulating film is stacked over the first insulating film;
in the third shallow trench isolation, the first insulating film and the second insulating film are embedded so that the second insulating film is stacked over the first insulating film; and
the first insulating film embedded in the third shallow trench isolation is thinner than the first insulating film embedded in the second shallow trench isolation.
8. The semiconductor device according to claim 7 , wherein
the second insulating film embedded in the third shallow trench isolation is thicker than the second insulating film embedded in the third shallow trench isolation.