Optimizing task management

1. An electronic device, comprising:

a processing array including a plurality of processing cores, the processing component being configurable for one of a single-core processing mode and a multi-core processing mode,

wherein the single-core processing mode comprises the processing array configured to execute an operating system in a first operating system mode using a first one of the processing cores, wherein the first operating system mode is optimized to perform a single task, and

wherein the multi-core processing mode comprises the processing array configured to execute the operating system in a second operating system mode using the first one of the processing cores and a second one of the processing cores, wherein the second operating system mode is optimized to perform multiple tasks; and

a task manager determining a number of user-operated tasks running on the electronic device,

wherein the processing array is configured to operate in the single-core processing mode or the multi-core processing mode based only on the number of user-operated tasks,

wherein the processing array operates in the single-core processing mode when the number of user-operated tasks is one and operates in the multi-core processing mode when the number of user-operated tasks is greater than one,

wherein the single-core processing mode enables only the single task to be executed and disables a multi-core processing architecture.

2. The electronic device of claim 1 , further comprising:

a memory for storing data of the electronic device.

3. The electronic device of claim 2 , further comprising:

a bus connecting the processing array to the memory to enable accessing of the memory.

4. The electronic device of claim 1 , wherein the processing array is a multiple-core processor.

5. The electronic device of claim 4 , wherein a single core of the multiple-core processor is used during the single-core processing mode.

6. The electronic device of claim 4 , wherein the multiple-core processor is one of a dual-core processor and a quad-core processor.

7. The electronic device of claim 1 , wherein the processing array is a plurality of single-core processors.

8. The electronic device of claim 7 , wherein at least two of the plurality of single-core processors are used for the multi-core processing mode and one of the plurality of single-core processors is used for the single-core processing mode.

9. A method, comprising:

determining a number of user-operated tasks running on an electronic device, the electronic device comprising a processing array including a plurality of processing cores, the processing array being configurable for one of a single-core processing mode and a multi-core processing mode,

wherein the single-core processing mode comprises the processing component configured to execute an operating system in a first operating system mode using a first one of the processing cores, wherein the first operating system mode is optimized to perform a single task, and

wherein the multi-core processing mode comprises the processing array configured to execute the operating system in a second operating system mode using the first one of the processing cores and a second one of the processing cores, wherein the second operating system mode is optimized to perform multiple tasks; and

configuring the processing array to operate in the single-core processing mode or the multi-core processing mode based only on the number of user-operated tasks,

wherein the processing array operates in the single-core processing mode when the number of user-operated tasks is one and operates in the multi-core processing mode when the number of user-operated tasks is greater than one,

wherein the single-core processing mode enables only the single task to be executed and disables a multi-core processing architecture.

10. The method of claim 9 , wherein the electronic device further comprises a memory for storing data of the electronic device.

11. The method of claim 10 , wherein the electronic device further comprises a bus connecting the processing array to the memory to enable accessing of the memory.

12. The method of claim 9 , wherein the processing array is a multi-core processor.

13. The method of claim 12 , wherein a single core of the multi-core processor is used during the single-core processing mode.

14. The method of claim 9 , wherein the processing array is a plurality of single-core processors.

15. The method of claim 14 , wherein at least two of the plurality of single-core processors are used for the multi-core processing mode and one of the plurality of single-core processors is used for the single-core processing mode.

16. A non-transitory computer readable storage medium with an executable program stored thereon, wherein the program instructs a processor to perform operations, comprising:

determining a number of user-operated tasks running on an electronic device, the electronic device comprising a processing array including a plurality of processing cores, the processing array being configurable for one of a single-core processing mode and a multi-core processing mode, wherein the single-core processing mode comprises the processing array configured to execute an operating system in a first operating system mode using a first one of the processing cores, wherein the first operating system mode is optimized to perform a single task, and wherein the multi-core processing mode comprises the processing array configured to execute the operating system in a second operating system mode using the first one of the processing cores and a second one of the processing cores, wherein the second operating system mode is optimized to perform multiple tasks; and

configuring the processing array to operate in the single-core processing mode or the multi-core processing mode based only on the number of user-operated tasks,

wherein the processing array operates in the single-core processing mode when the number of user-operated tasks is one and operates in the multi-core processing mode when the number of user-operated tasks is greater than one,

wherein the single-core processing mode enables only the single task to be executed and disables a multi-core processing architecture.