Isolating wire bonding in integrated electrical components
View Patent ↗An electrical component includes a semiconductor layer having a first conductivity type and a interconnect layer disposed adjacent to a frontside of the semiconductor layer. At least one bond pad is disposed in the interconnect layer and formed adjacent to the frontside of the semiconductor layer. An opening formed from the backside of the semiconductor layer and through the semiconductor layer exposes at least a portion of the bond pad. A first region having a second conductivity type extends from the backside of the semiconductor layer to the frontside of the semiconductor layer and surrounds the opening. The first region can abut a perimeter of the opening or alternatively, a second region having the first conductivity type can be disposed between the first region and a perimeter of the opening.
1. A method for isolating a wire affixed to a bond pad in an integrated circuit device, the method comprising:
forming a first region having a first conductivity type in a portion of a semiconductor layer, the semiconductor layer having a second conductivity type and having at least one integrated circuit formed therein, wherein the first region surrounds a portion of the semiconductor layer and extends from a backside of the semiconductor layer to a frontside of the semiconductor layer, and wherein the first conductivity type is opposite the second conductivity type;
forming an opening from the backside of the semiconductor layer through the semiconductor layer to expose at least a portion of a bond pad disposed in an interconnect layer formed on the frontside of the semiconductor layer, wherein the first region surrounds the opening; and
forming a well of the second conductivity type in the portion of the semiconductor layer surrounded by the first region.
2. The method as in claim 1 , further comprising thinning the semiconductor layer to a given thickness prior to forming the opening, wherein the first region and the well both extend from the backside of the thinned semiconductor layer to the frontside of the thinned semiconductor layer.
3. The method as in claim 2 , wherein forming an opening from a backside of the semiconductor layer through the semiconductor layer to expose at least a portion of the bond pad comprises forming an opening through a backside of the semiconductor layer through the well to expose at least a portion of the bond pad, wherein the remaining portion of the well abuts and surrounds a perimeter of the opening.
4. The method as in claim 1 , wherein forming an opening through a backside of the semiconductor layer through the semiconductor layer to expose at least a portion of the bond pad comprises forming an opening through a backside of the semiconductor layer through the surrounded portion of the semiconductor layer to expose at least a portion the bond pad such that the first region surrounds the opening but does not abut a perimeter of the opening.