IP Library Granted Patent US 8,341,487
Granted Patent B2
US 8,341,487 · App. 12/769,818 · Granted Dec 25, 2012

Low complexity communication device employing in-place constructed LDPC (low density parity check) code

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Quick Facts
Patent No.
US 8,341,487
App. No.
12/769,818
Granted
Dec 25, 2012
Kind
B2
Abstract

Low complexity communication device employing in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform decoding of more than one type of LDPC coded signals. A common basis of decoder hardware (e.g., decoder circuitry) is employed when decoding all of the various types of LDPC coded signals that such a communication device can decode. However, all of the decoder hardware is only employed to decode signals corresponding to the lowest code rate LDPC code supported by the communication device. A first subset of the decoder hardware is employed to decode signals corresponding to the second to lowest code rate LDPC code, a second subset (being less than the first subset) is employed to decode signals corresponding to the third to lowest code rate LDPC code, etc.

Claims (65)

1. An apparatus, comprising:

an LDPC (Low Density Parity Check) decoder circuitry for employing a plurality of configurations of a superimposed LDPC matrix for respectively decoding a plurality of LDPC coded signals, the superimposed LDPC matrix corresponding to LDPC codes of an in-place LDPC code set, wherein:

each of the LDPC codes having a respective code rate; and

each of the LDPC codes having a respective LDPC matrix; and

a switching module for, based on a selected LDPC code of the in-place LDPC code set, selectively enabling or disabling sub-matrices of the superimposed LDPC matrix for within each of the plurality of configurations; and wherein:

when the superimposed LDPC matrix being within a first of the plurality of configurations, the LDPC decoder circuitry decoding a first of the plurality of LDPC coded signals thereby generating a first plurality of information bit estimates; and

when the superimposed LDPC matrix being within a second of the plurality of configurations, the LDPC decoder circuitry decoding a second of the plurality of LDPC coded signals thereby generating a second plurality of information bit estimates.

2. The apparatus of claim 1 , wherein:

a first LDPC code of the in-place LDPC code set corresponding to a first code rate and a first LDPC matrix; and

a second LDPC code of the in-place LDPC code set corresponding to a second code rate, being higher than the first code rate, and corresponding to a second LDPC matrix, having fewer rows than the first LDPC matrix.

3. The apparatus of claim 2 , wherein:

the first LDPC matrix and the second LDPC matrix each include at least one common sub-matrix row.

4. The apparatus of claim 2 , wherein:

the first LDPC matrix and the second LDPC matrix each include at least one common sub-matrix column.

5. The apparatus of claim 2 , wherein:

a third LDPC code of the in-place LDPC code set corresponding to a third code rate, being higher than the second code rate, and corresponding to a third LDPC matrix, having fewer rows than the second LDPC matrix.

6. The apparatus of claim 1 , wherein:

the superimposed LDPC matrix being partitioned into a systematic matrix portion and a parity matrix portion; and

the parity matrix portion having a lower triangular form.

7. The apparatus of claim 1 , wherein:

the switching module switching between the first of the plurality of configurations and the second of the plurality of configurations in accordance with a predetermined sequence.

8. The apparatus of claim 1 , wherein:

the switching module switching between the first of the plurality of configurations and the second of the plurality of configurations based on a change in at least one operating condition of the apparatus or of a communication system in which the apparatus being implemented.

9. The apparatus of claim 1 , wherein:

each of the LDPC codes of the in-place LDPC code set being systematic.

10. The apparatus of claim 1 , wherein:

the apparatus being a communication device; and

the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

11. An apparatus, comprising:

an LDPC (Low Density Parity Check) decoder circuitry for employing a plurality of configurations of a superimposed LDPC matrix for respectively decoding a plurality of LDPC coded signals, the superimposed LDPC matrix corresponding to LDPC codes of an in-place LDPC code set, wherein:

each of the LDPC codes having a respective code rate;

each of the LDPC codes having a respective LDPC matrix;

each of the LDPC codes being systematic; and

the superimposed LDPC matrix being partitioned into a systematic matrix portion and a parity matrix portion such that the parity matrix portion having a lower triangular form; and

a switching module for, based on a selected LDPC code of the in-place LDPC code set, selectively enabling or disabling sub-matrices of the superimposed LDPC matrix for within each of the plurality of configurations; and wherein:

when the superimposed LDPC matrix being within a first of the plurality of configurations, the LDPC decoder circuitry decoding a first of the plurality of LDPC coded signals thereby generating a first plurality of information bit estimates;

when the superimposed LDPC matrix being within a second of the plurality of configurations, the LDPC decoder circuitry decoding a second of the plurality of LDPC coded signals thereby generating a second plurality of information bit estimates;

a first LDPC code of the in-place LDPC code set corresponding to a first code rate and a first LDPC matrix; and

a second LDPC code of the in-place LDPC code set corresponding to a second code rate, being higher than the first code rate, and corresponding to a second LDPC matrix, having fewer rows than the first LDPC matrix.

12. The apparatus of claim 11 , wherein:

the switching module switching between the first of the plurality of configurations and the second of the plurality of configurations in accordance with a predetermined sequence.

13. The apparatus of claim 11 , wherein:

the switching module switching between the first of the plurality of configurations and the second of the plurality of configurations based on a change in at least one operating condition of the apparatus or of a communication system in which the apparatus being implemented.

14. The apparatus of claim 11 , wherein:

the apparatus being a communication device; and

the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

15. A method for operating a communication device, the method comprising:

operating an LDPC (Low Density Parity Check) decoder circuitry for employing a plurality of configurations of a superimposed LDPC matrix for respectively decoding a plurality of LDPC coded signals, the superimposed LDPC matrix corresponding to LDPC codes of an in-place LDPC code set, wherein:

each of the LDPC codes having a respective code rate; and

each of the LDPC codes having a respective LDPC matrix;

based on a selected LDPC code of the in-place LDPC code set, selectively enabling or disabling sub-matrices of the superimposed LDPC matrix for within each of the plurality of configurations;

when the superimposed LDPC matrix being within a first of the plurality of configurations, operating the LDPC decoder circuitry for decoding a first of the plurality of LDPC coded signals thereby generating a first plurality of information bit estimates; and

when the superimposed LDPC matrix being within a second of the plurality of configurations, operating the LDPC decoder circuitry for decoding a second of the plurality of LDPC coded signals thereby generating a second plurality of information bit estimates.

16. The method of claim 15 , wherein:

a first LDPC code of the in-place LDPC code set corresponding to a first code rate and a first LDPC matrix; and

a second LDPC code of the in-place LDPC code set corresponding to a second code rate, being higher than the first code rate, and corresponding to a second LDPC matrix, having fewer rows than the first LDPC matrix.

17. The method of claim 15 , wherein:

the superimposed LDPC matrix being partitioned into a systematic matrix portion and a parity matrix portion; and

the parity matrix portion having a lower triangular form.

18. The method of claim 15 , further comprising:

switching between the first of the plurality of configurations and the second of the plurality of configurations in accordance with a predetermined sequence.

19. The method of claim 15 , further comprising:

switching between the first of the plurality of configurations and the second of the plurality of configurations based on a change in at least one operating condition of the communication device or of a communication system in which the communication device being implemented.

20. The method of claim 15 , wherein:

the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
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TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
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PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 3, 2010
From: BLANKSBY, ANDREW J.; SHEN, BA-ZHONG; TRACHEWSKY, JASON A.
To: BROADCOM CORPORATION
Reel/Frame 024324/0267 →