Communication device architecture for in-place constructed LDPC (low density parity check) code
View Patent ↗Communication device architecture for in-place constructed LDPC (Low Density Parity Check) code. Intelligent design of LDPC codes having similar characteristics there between allows for a very efficient hardware implementation of a communication device that is operative to perform encoding of respective information bit groups using more than one type of LDPC codes. A switching module can select any one of the LDPC codes within an in-place LDPC code for use by an LDPC encoder circuitry to generate an LDPC coded signal. Depending on which sub-matrices of a superimposed LDPC matrix are enabled or disabled, one of the LDPC matrices from within an in-place LDPC code matrix set may be selected. A corresponding, respective generator matrix may be generated from each respective LDPC matrix. Selection among the various LDPC codes may be in accordance with a predetermined sequence, of based operating conditions of the communication device or communication system.
1. An apparatus, comprising:
an LDPC (Low Density Parity Check) encoder circuitry to employ a plurality of configurations of a superimposed LDPC matrix respectively to encode respective pluralities of information bits thereby generating a plurality of LDPC coded signals, the superimposed LDPC matrix corresponding to LDPC codes of an in-place LDPC code set, wherein:
each of the LDPC codes having a respective code rate;
each of the LDPC codes having a respective LDPC matrix; and
each respective LDPC matrix corresponding to a respective generator matrix;
a switching module for, based on a selected LDPC code of the in-place LDPC code set, selectively enabling or disabling sub-matrices of the superimposed LDPC matrix within each of the plurality of configurations; and wherein:
when the superimposed LDPC matrix being within a first of the plurality of configurations, the LDPC encoder circuitry to employ a first generator matrix to encode a first respective plurality of information bits thereby generating a first of the plurality of LDPC coded signals; and
when the superimposed LDPC matrix being within a second of the plurality of configurations, the LDPC encoder circuitry to employ a second generator matrix to encode a second respective plurality of information bits thereby generating a second of the plurality of LDPC coded signals.
2. The apparatus of claim 1 , wherein:
a first LDPC code of the in-place LDPC code set corresponding to a first code rate, a first LDPC matrix, and the first generator matrix; and
a second LDPC code of the in-place LDPC code set corresponding to a second code rate, being higher than the first code rate, and corresponding to a second LDPC matrix, having fewer rows than the first LDPC matrix, and corresponding to the second generator matrix.
3. The apparatus of claim 2 , wherein:
a third LDPC code of the in-place LDPC code set corresponding to a third code rate, being higher than the second code rate, and corresponding to a third LDPC matrix, having fewer rows than the second LDPC matrix, and corresponding to a third generator matrix; and
when the superimposed LDPC matrix being within a third of the plurality of configurations, the LDPC encoder circuitry employing the third generator matrix for encoding a third respective plurality of information bits thereby generating a third of the plurality of LDPC coded signals.
4. The apparatus of claim 1 , wherein:
the superimposed LDPC matrix being partitioned into a systematic matrix portion and a parity matrix portion; and
the parity matrix portion having a lower triangular form.
5. The apparatus of claim 4 , wherein:
at least one of the first respective plurality of information bits and the second respective plurality of information bits including systematic bits and parity bits; and
the LDPC encoder circuitry performing back substitution thereby generating the parity bits.
6. The apparatus of claim 1 , wherein:
the switching module including a plurality of XOR gates and a plurality of AND gates; and
the switching module receiving a plurality of LDPC code selection signals corresponding to each of the LDPC codes of the in-place LDPC code set.
7. The apparatus of claim 1 , wherein:
the switching module switching between the first of the plurality of configurations and the second of the plurality of configurations in accordance with a predetermined sequence.
8. The apparatus of claim 1 , wherein:
the switching module switching between the first of the plurality of configurations and the second of the plurality of configurations based on a change in at least one operating condition of the apparatus or of a communication system in which the apparatus being implemented.
9. The apparatus of claim 1 , wherein:
each of the LDPC codes of the in-place LDPC code set being systematic.
10. The apparatus of claim 1 , wherein:
the apparatus being a communication device; and
the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
11. An apparatus, comprising:
an LDPC (Low Density Parity Check) encoder circuitry to employ a plurality of configurations of a superimposed LDPC matrix for respectively to encode respective pluralities of information bits thereby generating a plurality of LDPC coded signals, the superimposed LDPC matrix corresponding to LDPC codes of an in-place LDPC code set, wherein:
each of the LDPC codes having a respective code rate;
each of the LDPC codes having a respective LDPC matrix;
each respective LDPC matrix corresponding to a respective generator matrix;
each of the LDPC codes being systematic; and
the superimposed LDPC matrix being partitioned into a systematic matrix portion and a parity matrix portion such that the parity matrix portion having a lower triangular form;
a switching module for, based on a selected LDPC code of the in-place LDPC code set, selectively enabling or disabling sub-matrices of the superimposed LDPC matrix within each of the plurality of configurations; and wherein:
when the superimposed LDPC matrix being within a first of the plurality of configurations, the LDPC encoder circuitry to employ a first generator matrix to encode a first respective plurality of information bits thereby generating a first of the plurality of LDPC coded signals;
when the superimposed LDPC matrix being within a second of the plurality of configurations, the LDPC encoder circuitry to employ a second generator matrix to encode a second respective plurality of information bits thereby generating a second of the plurality of LDPC coded signals;
a first LDPC code of the in-place LDPC code set corresponding to a first code rate, a first LDPC matrix, and the first generator matrix; and
a second LDPC code of the in-place LDPC code set corresponding to a second code rate, being higher than the first code rate, and corresponding to a second LDPC matrix, having fewer rows than the first LDPC matrix, and corresponding to the second generator matrix.
12. The apparatus of claim 11 , wherein:
the switching module switching between the first of the plurality of configurations and the second of the plurality of configurations in accordance with a predetermined sequence.
13. The apparatus of claim 11 , wherein:
the switching module switching between the first of the plurality of configurations and the second of the plurality of configurations based on a change in at least one operating condition of the apparatus or of a communication system in which the apparatus being implemented.
14. The apparatus of claim 11 , wherein:
the apparatus being a communication device; and
the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
15. A method for operating a communication device, the method comprising:
operating an LDPC (Low Density Parity Check) encoder circuitry for employing a plurality of configurations of a superimposed LDPC matrix for respectively encoding respective pluralities of information bits thereby generating a plurality of LDPC coded signals, the superimposed LDPC matrix corresponding to LDPC codes of an in-place LDPC code set, wherein:
each of the LDPC codes having a respective code rate;
each of the LDPC codes having a respective LDPC matrix; and
each respective LDPC matrix corresponding to a respective generator matrix;
based on a selected LDPC code of the in-place LDPC code set, selectively enabling or disabling sub-matrices of the superimposed LDPC matrix for within each of the plurality of configurations;
when the superimposed LDPC matrix being within a first of the plurality of configurations, operating the LDPC encoder circuitry by employing a first generator matrix for encoding a first respective plurality of information bits thereby generating a first of the plurality of LDPC coded signals; and
when the superimposed LDPC matrix being within a second of the plurality of configurations, operating the LDPC encoder circuitry by employing a second generator matrix for encoding a second respective plurality of information bits thereby generating a second of the plurality of LDPC coded signals.
16. The method of claim 15 , wherein:
a first LDPC code of the in-place LDPC code set corresponding to a first code rate, a first LDPC matrix, and the first generator matrix; and
a second LDPC code of the in-place LDPC code set corresponding to a second code rate, being higher than the first code rate, and corresponding to a second LDPC matrix, having fewer rows than the first LDPC matrix, and corresponding to the second generator matrix.
17. The method of claim 15 , wherein:
the superimposed LDPC matrix being partitioned into a systematic matrix portion and a parity matrix portion;
the parity matrix portion having a lower triangular form; and
at least one of the first respective plurality of information bits and the second respective plurality of information bits including systematic bits and parity bits; and
further comprising:
operating the LDPC encoder circuitry by performing back substitution thereby generating the parity bits.
18. The method of claim 15 , further comprising:
switching between the first of the plurality of configurations and the second of the plurality of configurations in accordance with a predetermined sequence.
19. The method of claim 15 , further comprising:
switching between the first of the plurality of configurations and the second of the plurality of configurations based on a change in at least one operating condition of the communication device or of a communication system in which the communication device being implemented.
20. The method of claim 15 , wherein:
the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.