Self biased gate controlled switch
View Patent ↗Conventional current sharing circuits, which can be used in drivers for liquid crystal displays (LCDs), for example, often use bipolar transistors. However, bipolar transistors are not available in many CMOS processes. Thus, a current sharing circuit is provided here that employs CMOS transistors. In particular, the circuit provided here uses a current mirror and pass circuit to assist in providing this current sharing function.
1. An apparatus comprising:
a first pin;
a second pin;
a first MOS transistor that receives a first control signal at its gate;
a current mirror that is coupled to the drain of the first MOS transistor;
a second MOS transistor that is coupled to the current mirror at its source;
a pass circuit that is coupled between the first and second pins, wherein the pass circuit is coupled to the current mirror so as to receive a bias voltage, and wherein the pass circuit is coupled to the gate of the second MOS transistor so as to receive a control voltage, and wherein the pass circuit includes:
a third MOS transistor that is coupled to the first pin at it drain, that is coupled to the current mirror at its gate, and that is coupled to the gate of the second MOS transistor at its source; and
a fourth MOS transistor that is coupled to the second pin at it drain, that is coupled to the current mirror at its gate, and that is coupled to the gate of the second MOS transistor at its source;
a fifth MOS transistor that is coupled to the gate of the second MOS transistor at its drain and that receives a second control signal at is gate; and
a sixth MOS transistor that is coupled to the current mirror so as to receive the bias voltage at its drain and that receives the second control signal at is gate.
2. The apparatus of claim 1 , wherein the first, second, fifth, and sixth MOS transistors are first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, respectively.
3. The apparatus of claim 2 , wherein the third and fourth MOS further comprise a third NMOS transistor and a fourth NMOS transistor.
4. The apparatus of claim 1 , wherein the first, second, fifth, and sixth MOS transistors are first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor, respectively.
5. The apparatus of claim 4 wherein the third and fourth MOS further comprise a third PMOS transistor and a fourth NMOS transistor.
6. The apparatus of claim 5 , wherein the apparatus further comprises a Zener diode that is coupled between the source of second PMOS transistor and the current mirror.
7. The apparatus of claim 1 , wherein first and second level shifters provide the first and second control signals.
8. An apparatus comprising:
a first pin;
a second pin;
a first MOS transistor that receives a first control signal at its gate;
a current mirror that is coupled to the drain of the first MOS transistor;
a second MOS transistor that is coupled to the current mirror at its source;
a pass circuit that is coupled between the first and second pins, wherein the pass circuit is coupled to the current mirror so as to receive a bias voltage, and wherein the pass circuit is coupled to the gate of the second MOS transistor so as to receive a control voltage, and wherein the pass circuit includes:
a diode that is coupled between the gate of the first NMOS transistor and the first pin; and
a third MOS transistor that is coupled to the second pin at it drain, that is coupled to the current mirror at its gate, and that is coupled to the gate of the first NMOS transistor at its source;
a fourth MOS transistor that is coupled to the gate of the second MOS transistor at its drain and that receives a second control signal at its gate; and
a fifth MOS transistor that is coupled to the current mirror so as to receive the bias voltage at its drain and that receives the second control signal at its gate.
9. The apparatus of claim 8 , wherein the first, second, fourth, fifth, and third MOS transistors are first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, respectively.
10. An apparatus comprising:
a first pin;
a second pin;
a first buffer that is coupled to the first pin and that receives an enable signal and a first output signal, wherein the first buffer enters a high impedance state when the enable signal is asserted;
a second buffer that is coupled to the second pin and that receives the enable signal and a second output signal, wherein the enters buffer enters the high impedance state when the enable signal is asserted;
a current sharing circuit having:
an inverter that receives the enable signal;
a first level shifter that is coupled to the inverter;
a second level shifter that is coupled to
a first MOS transistor that is coupled to the first level shifter at its gate;
a current mirror that is coupled to the drain of the first MOS transistor;
a second MOS transistor that is coupled to the current mirror at its source;
a pass circuit that is coupled between the first and second pins, wherein the pass circuit is coupled to the current mirror so as to receive a bias voltage, and wherein the pass circuit is coupled to the gate of the second MOS transistor so as to receive a control voltage;
a third MOS transistor that is coupled to the gate of the second MOS transistor at its drain and that is coupled to the second level shifter at is gate; and
a fourth MOS transistor that is coupled to the current mirror so as to receive the bias voltage at its drain and that receives the second control signal at is gate.
11. The apparatus of claim 10 , wherein the first, second, third, and fourth MOS transistors are first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, respectively.
12. The apparatus of claim 11 , wherein the pass circuit further comprises:
a third NMOS transistor that is coupled to the first pin at it drain, that is coupled to the current mirror at its gate, and that is coupled to the gate of the second PMOS transistor at its source; and
a fourth NMOS transistor that is coupled to the second pin at it drain, that is coupled to the current mirror at its gate, and that is coupled to the gate of the second PMOS transistor at its source.
13. The apparatus of claim 11 , wherein the pass circuit further comprises:
a diode that is coupled between the gate of the first NMOS transistor and the first pin; and
a fifth NMOS transistor that is coupled to the second pin at it drain, that is coupled to the current mirror at its gate, and that is coupled to the gate of the first NMOS transistor at its source.
14. The apparatus of claim 10 , wherein the first, second, third, and fourth MOS transistors are first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor, respectively.
15. The apparatus of claim 14 , wherein the pass circuit further comprises:
a third PMOS transistor that is coupled to the first pin at it drain, that is coupled to the current mirror at its gate, and that is coupled to the gate of the second NMOS transistor at its source; and
a fourth NMOS transistor that is coupled to the second pin at it drain, that is coupled to the current mirror at its gate, and that is coupled to the gate of the second NMOS transistor at its source.
16. The apparatus of claim 15 , wherein the apparatus further comprises a Zener diode that is coupled between the source of second PMOS transistor and the current mirror.