Electrically isolated power semiconductor package with optimized layout
View Patent ↗A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.
1. A packaged power semiconductor device comprising:
a ceramic substrate having an upper and lower surface on opposite sides thereof;
an upper electrically conductive layer bonded to the upper surface of the ceramic substrate;
a lower electrically conductive layer bonded to the lower surface of the ceramic substrate;
a plurality of electrically conductive leads attached along an edge of the upper electrically conductive layer;
a generally rectangular power semiconductor device having a pair of longer sides and a pair of shorter sides, the generally rectangular power semiconductor device being attached to the upper electrically conductive layer in an orientation with the longer sides being parallel to the edge of the upper electrically conductive layer to which the plurality of electrically conductive leads are attached;
a region of encapsulating material disposed to cover the semiconductor device, the ceramic substrate and the upper electrically conductive layer, the encapsulant not covering a major surface of the lower electrically conductive layer, and leaving at least a portion of each of the plurality of electrically conductive leads exposed and extending from the encapsulant;
the encapsulating material extending away from the plurality of electrically conductive leads in a direction parallel to the edge of the upper electrically conductive layer to thereby provide an extended region of encapsulant having an upper surface, a lower surface, an end surface opposite the edge of the upper electrically conductive layer, and side surfaces;
a hole extending through the extended region of encapsulant from the upper surface to the lower surface of the extended region of encapsulant thereof to enable attachment of the packaged power semiconductor device to a mount; and
a first notch in the extended region of the encapsulant, the first notch extending into the encapsulant from the upper surface of the extended region of encapsulant and one of the side surfaces toward the hole, and extending toward the ceramic substrate.
2. The packaged power semiconductor device as in claim 1 further comprising a protrusion on the lower surface of the extended region of encapsulant at the end surface.
3. The packaged power semiconductor device as in claim 2 wherein the protrusion extends across the lower surface of the encapsulant at the end surface.
4. The packaged power semiconductor device as in claim 3 wherein the protrusion comprises a series of separated regions extending from the lower surface of the encapsulant.
5. The packaged power semiconductor device as in claim 1 further comprising a second notch extending into the encapsulant from the upper surface of the extended region encapsulant and another of the side surfaces toward the hole, and extending toward the ceramic substrate.
6. The packaged power semiconductor device as in claim 1 wherein the encapsulant is configured in a TO-247 package configuration.
7. The packaged power semiconductor device as in claim 1 wherein:
the semiconductor die includes an insulated gate bipolar transistor (IGBT); and
the plurality of electrically conductive leads attached along an edge of the upper electrically conductive layer include three leads with a first lead soldered to the upper electrically conductive layer, and second and third leads wire bonded to the IGBT.
8. The packaged power semiconductor device as in claim 2 further comprising:
a heat sink;
an attaching device which extends through the hole to secure the packaged power semiconductor device to the heat sink, and wherein
the protrusion allows the attaching device to bias the lower electrically conductive layer against the heat sink to enable improved thermal conductivity.
9. The packaged power semiconductor device as in claim 8 wherein the attachment device comprises a threaded fastener which pulls the packaged power semiconductor device against the heat sink.
10. The packaged power semiconductor device as in claim 1 wherein the ceramic substrate comprises alumina and each of the upper electrically conductive layer and the lower electrically conductive layer comprise copper.
11. The packaged power semiconductor device as in claim 10 wherein the generally rectangular power semiconductor device is attached to the upper electrically conductive layer with solder.
12. A packaged power semiconductor device comprising:
a ceramic substrate having an upper and lower surface on opposite sides thereof;
an upper electrically conductive layer bonded to the upper surface of the ceramic substrate;
a lower electrically conductive layer bonded to the lower surface of the ceramic substrate;
a plurality of electrically conductive leads attached along an edge of the upper electrically conductive layer;
a semiconductor device attached to the upper electrically conductive layer, the semiconductor device having a longer dimension arranged to be parallel to the edge of the upper electrically conductive layer;
a region of encapsulating material disposed to cover the semiconductor device, the ceramic substrate and the upper electrically conductive layer, the encapsulant not covering a major surface of the lower electrically conductive layer, and leaving at least a portion of each of the plurality of electrically conductive leads exposed and extending from the encapsulant;
the encapsulating material extending away from the plurality of electrically conductive leads in a direction parallel to the edge of the upper electrically conductive layer to thereby provide an extended region of encapsulant having an upper surface, a lower surface, an end surface opposite the edge of the upper electrically conductive layer, and side surfaces;
a hole extending through the extended region of encapsulant from the upper surface of the extended region of encapsulant to the lower surface of the extended region of encapsulant thereof to enable attachment of the packaged power semiconductor device to a mount; and
a protrusion on the lower surface of the extended region of encapsulant at the end surface; a first notch in the extended region of the encapsulant, the first notch extending into the encapsulant from the upper surface of the extended region encapsulant and one of the side surfaces toward the hole, and extending toward the ceramic substrate.
13. The packaged power semiconductor device as in claim 12 wherein the protrusion extends across the lower surface of the extended region encapsulant between the side surfaces at the end surface.
14. A packaged power semiconductor insulated gate bipolar transistor (IGBT) device comprising:
a direct bonded copper substrate including a ceramic substrate having an upper and lower surface on opposite sides thereof;
a first copper layer bonded to the upper surface of the ceramic substrate;
a second copper layer bonded to the lower surface of the ceramic substrate;
three electrically conductive leads attached along an edge of the first copper layer;
an IGBT semiconductor device having a pair of longer sides and a pair of shorter sides, the IGBT being soldered to the upper electrically conductive layer in an orientation with the longer sides being parallel to the edge of the first copper layer to which the three electrically conductive leads are attached;
a region of encapsulating material disposed in a TO-247 compliant format to cover the IGBT, the ceramic substrate and the first copper layer, the encapsulant not covering a bottom surface of the second copper layer, and leaving at least a portion of each of the three electrically conductive leads exposed and extending from the encapsulant;
the encapsulating material extending away from the three electrically conductive leads in a direction parallel to the edge of the first copper layer to thereby provide an extended region of encapsulant;
a hole extending through the extended region of encapsulant from an upper surface of the extended region of encapsulant to a lower surface of the extended region of encapsulant thereof to enable attachment of the packaged power semiconductor device to a heat sink; and
a protrusion on the lower surface of the extended region of encapsulant to facilitate improved thermal contact between the bottom surface of the second copper layer and the heat sink when the packaged power semiconductor insulated gate bipolar transistor (IGBT) device is affixed to the heat sink a first notch in the extended region of the encapsulant, the first notch extending into the encapsulant from the upper surface of the extended region encapsulant and one of the side surfaces toward the hole, and extending toward the ceramic substrate.