Low distortion MOS attenuator
View Patent ↗An attenuation circuit uses a voltage controlled variable resistance transistor as a signal attenuator for receivers operating in the zero Hz to about 30 MHz range. The transistor functions in the linear region to linearize the transistor resistance characteristics used for signal attenuation. In an exemplary application, the attenuation circuit is used as an RF attenuator for AM radio broadcast receivers and amplifiers with automatic gain control. Multiple attenuation circuits can be coupled in parallel, each attenuation circuit having a different sized variable resistance transistor, to form sequentially activated stages that increase the range of attenuation while minimizing distortion.
1. A method of attenuating a signal, the method comprising:
a. attenuating the signal using a field-effect transistor as a variable resistor, the field-effect transistor having a source, a gate and a drain, the source and drain being coupled across the attenuated signal;
b. scaling the attenuated signal; and
c. combining the scaled attenuated signal with a variable DC bias signal and applying the combination to the gate of the field-effect transistor, thereby adjusting a resistance of the field-effect transistor attenuating the signal responsive to the combination of the variable DC bias signal and the scaled attenuated signal.
2. The method of claim 1 wherein the coupled scaling circuit comprises a DC coupled amplifier.
3. The method of claim 1 wherein the signal comprises a radio frequency signal.
4. The method of claim 1 wherein a frequency of the signal ranges from about zero Hz to about 30 MHz.
5. The method of claim 1 wherein the field-effect transistor comprises a metal-oxide-semiconductor field-effect transistor.
6. The method of claim 1 further comprising receiving the signal by an antenna.
7. The method of claim 1 further comprising supplying the attenuated signal to an amplifier coupled as the scaling circuit.
8. The method of claim 1 further comprising adjusting the DC bias signal to adjust the resistance of the field-effect transistor, thereby adjusting the attenuation of the signal.
9. The method of claim 1 wherein the coupled scaling circuit comprises an active circuit.
10. The method of claim 1 wherein the coupled scaling circuit comprises a passive circuit.
11. The method of claim 1 wherein the field-effect transistor is coupled to provide a shunt resistance to the signal.
12. The method of claim 1 wherein the field-effect transistor, the scaling circuit, and the variable DC bias circuit form an attenuation circuit, and the method further comprises coupling a plurality of attenuation circuits in parallel, each of the field-effect transistors in the plurality of attenuation circuits having a different maximum resistance, and wherein the signal is attenuated according to a shunt resistance resulting from an instantaneous resistance of all of the field-effect transistors of the attenuation circuits coupled in parallel.
13. The method of claim 12 wherein the plurality of attenuation circuits are configured as cascading stages, the field-effect transistors plurality of stages being turned on sequentially in descending order of maximum resistance starting with a first field-effect transistor having a highest maximum resistance and ending with a last field-effect transistor having a lowest maximum resistance.
14. The method of claim 13 wherein the field-effect transistor in each successive stage is turned on only after the transistor in the previous stage is fully turned on.
15. The method of claim 1 wherein the scaling is selected to reduce distortion of the attenuated signal in comparison to the distortion that would be obtained by simply applying the variable DC bias signal to the gate of the field-effect transistor.
16. The method of claim 1 wherein the scaling is a fixed fraction of the attenuated signal selected to reduce distortion of the attenuated signal in comparison to the distortion that would be obtained by simply applying the variable DC bias signal to the gate of the field-effect transistor.