Device and method for transient voltage suppressor
A transient voltage suppressor (TVS) device includes a semiconductor substrate of a first conductivity type, and a first and a second semiconductor regions of a second conductivity type overlying the semiconductor substrate. A semiconductor layer of the second conductivity type overlies the first and the second semiconductor regions. The TVS device has a first trench extending through the semiconductor layer and the first semiconductor region and into the semiconductor substrate, and a fill material of the second conductivity type disposed in the first trench. A clamping diode in the TVS device has a junction between an out-diffused region from the fill material and a portion of the semiconductor substrate. The TVS device also includes a first P-N diode formed in a first portion of the semiconductor layer, and a second P-N diode having a junction between the second semiconductor region and the semiconductor substrate.
1. A transient voltage suppressor (TVS) device, comprising:
a p-type semiconductor substrate;
a first and a second n-type semiconductor regions overlying the semiconductor substrate, the first region having a first doping concentration and the second region having a second doping concentration that is lower than the first doping concentration;
an n-type semiconductor layer overlying the first and the second n-type semiconductor regions;
a plurality of trenches extending through the n-type semiconductor layer and the first n-type semiconductor region and into the p-type semiconductor substrate;
an n-type fill material disposed in each of the plurality of trenches;
a clamping diode having a junction region between out-diffused regions from the n-type fill material and a portion of the p-type semiconductor substrate, wherein:
the clamping diode is coupled in parallel with a diode junction between the first n-type semiconductor region and the p-type semiconductor substrate, and
the clamping diode is configured to have a clamping voltage lower than a reverse breakdown voltage of said junction such that said junction is prevented from functioning as a Zener diode;
a PIN diode including a p-type region, a first portion of the n-type semiconductor layer, and the first n-type semiconductor region;
an NIP diode including an n-type region, a second portion of the n-type semiconductor layer, the second n-type semiconductor region, and the p-type semiconductor substrate;
a first isolation region around the PIN diodes;
a second isolation region around the NIP diodes; and
a conductor coupling the n-type fill material disposed in each of the trenches.
2. The device of claim 1 , wherein the fill material is in direct contact with the first semiconductor layer through a trench sidewall.
3. The device of claim 1 , wherein the fill material comprises polysilicon.
4. The device of claim 1 , wherein the fill material comprises a doped silicide material.
5. The device of claim 1 , wherein each of the first and the second isolation regions comprises a trench isolation region.
6. A transient voltage suppressor (TVS) device, comprising:
a semiconductor substrate of a first conductivity type;
a first and a second semiconductor regions of a second conductivity type overlying the semiconductor substrate, the first region having a first doping concentration and the second region having a second doping concentration;
a semiconductor layer of the second conductivity type overlying the first and the second semiconductor regions;
a first trench extending through the semiconductor layer and the first semiconductor region and into the semiconductor substrate;
a fill material of the second conductivity type disposed in the first trench;
a clamping diode having a junction between an out-diffused region from the fill material and a portion of the semiconductor substrate;
a first P-N diode formed in a first portion of the semiconductor layer;
a second P-N diode having a junction between the second semiconductor region and the semiconductor substrate; and
an isolation region separating the first and the second P-N diodes.
7. The device of claim 6 , wherein:
the clamping diode is coupled in parallel with a junction formed between the first semiconductor region and the semiconductor substrate; and
the clamping diode is configured to have a clamping voltage lower than a reverse breakdown voltage of said junction such that said junction is prevented from functioning as a Zener diode.
8. The device of claim 6 , wherein the first P-N diode is disposed overlying the first semiconductor region.
9. The device of claim 6 , wherein the fill material is in direct contact with the first semiconductor layer through a trench sidewall.
10. The device of claim 6 , wherein the first trench is free from a dielectric layer on the trench sidewalls.
11. The device of claim 6 , wherein the clamping diode has a Zener voltage of 7.0 V or lower.
12. The device of claim 6 , wherein the isolation region comprises a trench isolation region enclosing the second P-N diode.
13. The device of claim 6 , wherein:
the first conductivity type is p-type;
the second conductivity type is n-type;
the first P-N diode comprises a PIN diode; and
the second P-N diode comprises an NIP diode.
14. The device of claim 6 , wherein:
the first conductivity type is n-type;
the second conductivity type is p-type;
the first P-N diode comprises a NIP diode; and
the second P-N diode comprises an PIN diode.
15. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type;
a semiconductor layer of a second conductivity type overlying the semiconductor substrate;
a first trench extending through the semiconductor layer into the semiconductor substrate;
a fill material of the second conductivity type disposed in the first trench; and
a clamping diode having a junction between an out-diffused region from the fill material and a portion of the semiconductor substrate.
16. The device of claim 15 , wherein the fill material is in direct contact with the first semiconductor layer through a trench sidewall.
17. The device of claim 15 , wherein the first trench is free from a dielectric layer on the trench sidewalls.
18. The device of claim 15 , wherein the isolation region comprises a trench isolation region enclosing the second P-N diode.
19. The device of claim 15 , further comprising:
a first region in the semiconductor layer and being in contact with the first trench;
a second region in the semiconductor layer and being in contact with the semiconductor substrate, but not in contact the first trench;
a first P-N diode formed in the first region;
a second P-N diode formed by the second region and the semiconductor substrate; and
an isolation region separating the first P-N diode and the second P-N diode.
20. The device of claim 19 , wherein the first region comprises a buried region in contact with the semiconductor substrate.
21. The device of claim 20 , wherein the first P-N diode is disposed overlying the buried region.
22. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type and having a first doping concentration;
a first semiconductor layer of a second conductivity type overlying the semiconductor substrate, the first semiconductor layer having a second doping concentration;
a doped conductive material extending through the first semiconductor layer into the semiconductor substrate; and
a clamping diode formed by the doped conductive material and a portion of the semiconductor substrate.
23. The device of claim 22 , wherein the clamping diode comprises a junction between an out-diffused region from the doped conductive material and a region in the semiconductor substrate.
24. The device of claim 22 , wherein the clamping diode has a Zener voltage of 7.0 V or lower.
25. The device of claim 22 , wherein the doped conductive material comprises a silicon containing material.
26. A method for forming a transient voltage suppressor (TVS) device, comprising:
providing a semiconductor substrate of a first conductivity type;
forming a first and a second semiconductor regions of a second conductivity type overlying the semiconductor substrate, the first region having a first doping concentration and the second region having a second doping concentration;
forming a semiconductor layer of the second conductivity type overlying the first and the second semiconductor regions;
forming a first trench extending through the semiconductor layer and the first semiconductor region and into the semiconductor substrate;
disposing a fill material of the second conductivity type in the first trench; and
forming a clamping diode at a junction between the fill material and the semiconductor substrate.
27. The method of claim 26 , wherein disposing the fill material of the second conductivity type in the first trench comprises depositing a polysilicon material.
28. The method of claim 26 , wherein forming the clamping diode comprises using a thermal process to form a clamping diode junction between an out-diffused region and a region in the semiconductor substrate.
29. The method of claim 28 , wherein forming a first trench comprises forming the first trench to a selected depth into the semiconductor substrate such that the dopant concentration of the semiconductor substrate is higher at the clamping diode junction than is at a junction formed between the first semiconductor region and the semiconductor substrate.
30. The method of claim 26 , further comprising:
forming a first P-N diode formed in a first portion of the semiconductor layer; and
forming a second P-N diode having a junction between the second semiconductor region and the semiconductor substrate.
31. The method of claim 30 , further comprising forming an isolation region separating the first and the second P-N diodes.
32. The method of claim 30 , wherein the isolation region comprises a trench isolation region enclosing the second P-N diode.